무선통신소자제작을 위한 45GHz $f_{T}$ 및 50GHZz $f_{max}$ SiGe BiCMOS 개발

황석희,조대형,박강욱,이상돈,김남주,Hwang Seok-Hee,Cho Dae-Hyung,Park Kang-Wook,Yi Sang-Don,Kim Nam-Ju 대한전자공학회 2005 電子工學會論文誌-SD (Semiconductor and devices) Vol.42 No.9

최근 Mobile용 RF ICs 적용을 위한 RF CMOS 기술과 함께 핵심 기술로 SiGe Heterojunction Bipolar Transistor (HBT) 소자 개발의 중요성이 증대되고 있다. 본 논문은 현재 5GHz 동작 수준의 RF제품에서 주로 사용되는 기술인 $0.35\{mu}m$ 설계 Rule을 적용하여 $f_{max}$ 50GHz에서 동작하는 SiGe BiCMOS 기술 개발에 대한 내용을 논의한다. 본 SiGe HBT에 사용하는 에피막 성장 기술은 Trapezoidal Ge base profile 및 non-selective 방식이고, 에미터 RTA 조건 및 SiGe HBT base에 대한 Vertical Profile 최적화를 수행하였다. hFE 100, $f_{T}\;45GHz,\;NF_{min}\;0.8dB$ 수준으로 우수한 특성 및 기술 경쟁력을 갖는 SiGe BiCMOS 공정 개발 및 양산 기술을 확보하였다. 또한, 기존의 0.35um설계 Rule공정 target떼 부합되는 CMOS소자를 포함시켰으며, RF용 Passive소자로 높은 Q값을 갖는 MIM capacitor(1pF, Q>80), Inductor(2nH $Q\~$l2.5)를 제공하였다 A $0.35\mu$m SiGe BiCMOS fabrication process has been timely developed, which is aiming at wireless RF ICs development and fast growing SiGe RF market. With non-selective SiGe epilayer, SiGe HBTs in this process used trapezoidal Ge base profile for the enhanced AC performance via Ge induced bandgap niuoin. The characteristics of hFE 100, $f_{T}\;45GHz,\;F_{max}\;50GHz,\;NF_{min}\;0.8dB$ have been obtained by optimizing not only SiGe base profile but also RTA condition after emitter polysilicon deposition, which enables the SiGe technology competition against the worldwide cutting edge SiGe BiCMOS technology. In addition, the process incorporates the CMOS logic, which is fully compatible with $0.35\mu$m pure logic technology. High Q passive elements are also provided for high precision analog circuit designs, and their quality factors of W(1pF) and inductor(2nH) are 80, 12.5, respectively.

Epilayer Optimization of NPN SiGe HBT with n+ Buried Layer Compatible With Fully Depleted SOICMOS Technology

Prasanna Kumar Misra,S. Qureshi 대한전자공학회 2014 Journal of semiconductor technology and science Vol.14 No.3

In this paper, the epi layer of npn SOI HBT with n+ buried layer has been studied through Sentaurus process and device simulator. The doping value of the deposited epi layer has been varied for the npn HBT to achieve improved ftBVCEO product (397 GHzV). As the BVCEO value is higher for low value of epi layer doping, higher supply voltage can be used to increase the ft value of the HBT. At 1.8 V VCE, the ftBVCEO product of HBT is 465.5 GHzV. Further, the film thickness of the epi layer of the SOI HBT has been scaled for better performance (426.8 GHzV ftBVCEO product at 1.2 V VCE). The addition of this HBT module to fully depleted SOI CMOS technology would provide better solution for realizing wireless circuits and systems for 60 GHz short range communication and 77 GHz automotive radar applications. This SOI HBT together with SOI CMOS has potential for future high performance SOI BiCMOS technology.

SiGe HBT 를 이용한 PCS 단말기용 전력소자의 설계 및 전력증폭기의 구현

윤상웅 경희-다반 ASIC 설계교육센터 2007 경희-다반 ASIC센터 논문집 Vol.8 No.-

본 논문에서는 SiGe HBT (Heterojunction Bioloar Transistor) 를 이용하여 PCS 단말기용 전략소자들응 설계하였고 이 소자들로 구성된 전략증폭기를 구현하였다. 전력소자를 설계함에 있어서 distributed lumped 모델을 개발하여 이 용하였다. 이 모델은 MEXTRAM 504 모텔을 이용하여 단위 소자인 SiGe HBT를 모델링하였고 수십 개의 단위 소자를 병렬로 연결하는 전략소자의 연결선들은 RLC를 사용한 distributed lumped모델링을 하였다 .전력증폭기는 두 개의 스테이지로 구성히였는데 첫 번째 스테이지는 전력증폭기의 이득을 얻는 부분이고 두번째 스테이지는 전력을 얻는 부분이므로 사용된 전략소자외 크기의 비는 1:4 로 설계되었다. 전력증폭기를 구현함에 었어 설계된 진력소자를 패키징하여 사용하였다. 메이스와 컬렉터의 바이어스는 λ/4-전송 선로를 이용하여 RF 신호에 대한 open 을 만들어서 가하였다. 입력매칭, 출력매칭 회로는 전송선로와 병렬 캐패시터를 이용한 저주파 필터 형 태의 매칭 회로로 설계하였으며 인터스테이지 매칭 회로는 고주파 필터 형태의 매칭 회로로 설계하여 전체적으로 대역동과 필터 형태의 특성을 가지도록 했다. 주파수는 1.88 GHz에서 측정하였으며 공급전압은 3.3V 이고 ICQ 는 60mA 를 보였다. 선형성을 나타내는 P1dB는 28 dBm이고 이 때의 컬렉터 전류는 397mA 로 PAE 는 49 % 로 계산 되었다. P1dB 점에서의 이득은24.3 dB 로 측정되었다. 중심수파수에서885 KHz 와 1.25 MHz 떨어진 오프세트에서의 ACPR tnecajA( Channel Power Ratio)은 각각 -35 dBc와 -42 dBc로 측정되어 PCS 용 단말기에 사용 될 수 있음을 보였다.

Bottom 컬렉터와 단일 금속층 구조로 설계된 SiGe HBT의 전기적 특성

최아람,최상식,김준식,윤석남,김상훈,심규환,Choi, A-Ram,Choi, Sang-Sik,Kim, Jun-Sik,Yoon, Seok-Nam,Kim, Sang-Hoon,Shim, Kyu-Hwan 한국전기전자재료학회 2007 전기전자재료학회논문지 Vol.20 No.8

This paper presents the electrical properties of SiGe HBTs designed with bottom collector and single metal layer structure for RF power amplifier. Base layer was formed with graded-SiGe/Si structures and the collector place to the bottom of the device. Bottom collector and single metal layer structures could significantly simplify the fabrication process. We studied about the influence of SiGe base thickness, number of emitter fingers and temperature dependence $(<200^{\circ}C)$ on electrical properties. The feasible application in $1{\sim}2GHz$ frequency from measured data $BV_{CEO}{\sim}10V,\;f_T{\sim}14GHz,\;{\beta}{\simeq}110,\;NF{\sim}1dB$ using packaged SiGe HBTs. We will discuss the temperature dependent current flow through the e-b, b-c junctions to understand stability and performance of the device.

Epilayer Optimization of NPN SiGe HBT with n+ Buried Layer Compatible With Fully Depleted SOI CMOS Technology

Misra, Prasanna Kumar,Qureshi, S. The Institute of Electronics and Information Engin 2014 Journal of semiconductor technology and science Vol.14 No.3

In this paper, the epi layer of npn SOI HBT with n+ buried layer has been studied through Sentaurus process and device simulator. The doping value of the deposited epi layer has been varied for the npn HBT to achieve improved $f_tBV_{CEO}$ product (397 GHzV). As the $BV_{CEO}$ value is higher for low value of epi layer doping, higher supply voltage can be used to increase the $f_t$ value of the HBT. At 1.8 V $V_{CE}$, the $f_tBV_{CEO}$ product of HBT is 465.5 GHzV. Further, the film thickness of the epi layer of the SOI HBT has been scaled for better performance (426.8 GHzV $f_tBV_{CEO}$ product at 1.2 V $V_{CE}$). The addition of this HBT module to fully depleted SOI CMOS technology would provide better solution for realizing wireless circuits and systems for 60 GHz short range communication and 77 GHz automotive radar applications. This SOI HBT together with SOI CMOS has potential for future high performance SOI BiCMOS technology.

SiGe HBT의 Current Gain 특성 향상

송오성,이상돈,김득중 한국산학기술학회 2004 한국산학기술학회논문지 Vol.5 No.4

초고속 RF IC의 핵심소자인 SiGe 에피텍시층을 가진 이종양극트란지스터(hetero junction bipolar transistor: HBT)를 0.35㎛급 Si-Ge BiCMOS공정으로 제작하였다. 낮은 VBE영역에서의 current gain의 선형성을 향상시키기 위하여 SiGe 에피텍시층의 결함밀도를 감소시킬 수 있는 캐핑실리콘의 두께와 EDR 온도의 최적화 공정조건을 알아보았다. 캐핑 실리콘의 두께를 200Å과 300Å으로 나누고 초고속 무선통신에서 요구되는 낮은 노이즈를 위한 EDR(Emitter Drive-in RTA)의 온 도와 시간을 900~1000℃, 0~30 sec로 각각 변화시키면서 최적조건을 확인하였다 실험범위 내에서의 최적공정조건은 300A의 capping 실리콘과 975℃~30sec의 EDR 조건을 확인하였다. We fabricated SiGe BiCMOS devices, which are important for ultra high speed RF IC chips, by employing 0.35 ㎛ CMOS process. To meet with the requirement of low noise level with linear base leakage current at low VBE region, we try to minimize polysilicon/silicon silicon interface traps by optimizing capping silicon thickness and EDR(emitter drive-in RTA) temperature. We employed 200Å and 300Å-thick capping silicon, and varied the EDR process condition at temperature of 900~1000℃, and time of 0~30 sec at a given capping silicon thickness. We investigated current gain behavior at each process condition. We suggest that optimum EDR process condition would be 975℃~30 sec with 300 Å-thick capping silicon for proposed 0.35 ㎛-Sifle HBT devices.

X-대역 SiGe HBT 직접변환 주파수 혼합기 MMIC 설계

서정욱,김창우 경희-다반 ASIC 설계교육센터 2004 경희-다반 ASIC센터 논문집 Vol.5 No.-

X-band용 직접변환방식에 사용할 수 있는 상향주파수 혼합기를 SiGe HBT를 이용하여 설계하였다. 상향주파수혼합기는 이중평형형형태로 설계하였으며, 하향주파수혼합기는 직접변환방식에서의 문제점인 LO 누설을 억압하기 위하여 LO주파수 대신 LO 주파수의 1/2배인 주파수를 사용한 서브하모닉 주파수 혼합기형태로 설계하였다. 설계된 상향주파수 혼합기는 LO-RF 격리도 44.8 dB, IF-RF 격리도 32.8 dB. 변환이득 7.05 dB를 얻었으며 하향주파수 혼합기로 설계된 SDBM는 LO-lF 격리도 44.1 dB, LO-RF 격리도 73.7 변환이득 17.7 dB를 얻었다.

Monolithic SiGe HBT Feedforward Variable Gain Amplifiers for 5 GHz Applications

Chang-Woo Kim 한국전자통신연구원 2006 ETRI Journal Vol.28 No.3

Monolithic SiGe heterojunction bipolar transistor (HBT) variable gain amplifiers (VGAs) with a feedforward configuration have been newly developed for 5 GHz applications. Two types of the feedforward VGAs have been made: one using a coupled-emitter resistor and the other using an HBT-based current source. At 5.2 GHz, both of the VGAs achieve a dynamic gain-control range of 23 dB with a controlvoltage range from 0.4 to 2.6 V. The gain-tuning sensitivity is 90 mV/dB. At VCTRL= 2.4 V, the 1 dB compression output power, P1-dB, and dc bias current are 0 dBm and 59 mA in a VGA with an emitter resistor and -1.8 dBm and 71mA in a VGA with a constant current source, respectively.

RPCVD를 이용한 실리콘 게르마늄 이종 접합 바이폴라 트랜지스터 제작 및 특성 분석

한태현,서광열 한국전기전자재료학회 2004 전기전자재료학회논문지 Vol.17 No.8

In this paper, non-self-aligned SiGe HBTs with ${f}_\tau$ and${f}_max $above 50 GHz have been fabricated using an RPCVD(Reduced Pressure Chemical Vapor Deposition) system for wireless applications. In the proposed structure, in-situ boron doped selective epitaxial growth(BDSEG) and TiSi$_2$ were used for the base electrode to reduce base resistance and in-situ phosphorus doped polysilicon was used for the emitter electrode to reduce emitter resistance. SiGe base profiles and collector design methodology to increase ${f}_\tau$ and${f}_max $ are discussed in detail. Two SiGe HBTs with the collector-emitter breakdown voltages ${BV}_CEO$ of 3 V and 6 V were fabricated using SIC(selective ion-implanted collector) implantation. Fabricated SiGe HBTs have a current gain of 265 ∼ 285 and Early voltage of 102 ∼ 120 V, respectively. For the $1\times{8}_\mu{m}^2$ emitter, a SiGe HBT with ${BV}_CEO$= 6 V shows a cut-off frequency, ${f}_\tau$of 24.3 GHz and a maximum oscillation frequency, ${f}_max $of 47.6 GHz at $I_c$of 3.7 mA and$V_CE$ of 4 V. A SiGe HBT with ${BV}_CEO$ = 3 V shows ${f}_\tau$of 50.8 GHz and ${f}_max $ of 52.2 GHz at $I_c$ of 14.7 mA and $V_CE$ of 2 V.

SiGe HBT 제작을 위한 실리콘 게르마늄 단결정 박막의 RBS 분석

한태현,안호명,서광열 한국전기전자재료학회 2004 전기전자재료학회논문지 Vol.17 No.9

In this paper, the strained Si$_{0.9}$Ge$_{0.1}$ epitaxial layers grown by a reduced pressure chemical vapor deposition (RPCVD) on Si (100) were characterized by Rutherford backscattering spectrometery (RBS) for the fabrication of an SiGe heterojunction bipolar transistor(HBT). RBS spectra of the ${Si}_0.9{Ge}_0.1$epitaxial layers grown on the Si substrates which were implanted with the phosphorus (P) ion and annealed at a temperature between $850^{\circ}C$ - $1000^{\circ}C$ for 30min were analyzed to investigate the post thermal annealing effect on the grown${Si}_0.9{Ge}_0.1$epitaxial layer quality. Although a damage of the substrates by P ion-implantation might be cause of the increase of RBS yield ratios, but any defects such as dislocation or stacking fault in the grown ${Si}_0.9{Ge}_0.1$ epitaxial layer were not found in transmission electron microscope (TEM) photographs. The post high temperature rapid thermal annealing (RTA) effects on the crystalline quality of the ${Si}_0.9{Ge}_0.1$ epitaxial layers were also analyzed by RBS. The changes in the RBS yield ratios were negligible for RTA a temperature between $900^{\circ}C$ - $1000^{\circ}C$for 20 sec, or $950^{\circ}C$for 20 sec - 60 sec. A SiGe HBT array shows a good Gummel characteristics with post RTA at $950^{\circ}C$ for 20 sec.sec.sec.