Optimization of pick-and-place in die attach process using a genetic algorithm

Park, You-Jin,Ahn, Gilseung,Hur, Sun Elsevier 2018 Applied soft computing Vol.68 No.-

<P><B>Abstract</B></P> <P>The entire semiconductor manufacturing process can be largely divided into two sequential sub-processes that are commonly referred to as front-end and back-end production. Both production processes involve many complicated and elaborate steps for wafer fabrication, probe testing and sorting, assembly, final test, etc. The front-end process refers to wafer fabrication process, whereas the back-end process refers to the assembly, packaging, and testing of individual semiconductor devices. Once the front-end process is complete, the wafers are transferred to the back-end process in order to facilitate its integration into electronic devices and to take final performance test. In back-end production process, based on quality and location information of individual chip (die) derived from the EDS process, only good semiconductor chips (dies) are individually picked up by an automatic robot arm and then attached to the support structure (e.g., the lead frame) on a strip. This process is called die attach process. In order to improve the production efficiency of die attach process, it is necessary to evaluate various robot arm operation methods (rules) and then to provide the most efficient operation method since the total transfer distance (or total transfer time) considerably depends on the robot arm operation methods as well as the distribution of good chips on wafers. Thus, in this research, a pick-and-place problem of the die attach process is mathematically formulated and several transfer methods are compared.</P> <P><B>Highlights</B></P> <P> <UL> <LI> The die attach process in semiconductor back-end production is considered. </LI> <LI> A genetic algorithm (GA) based on binary integer programming (BIP) is proposed to find optimal (or near optimal) pick-and-place (PAP) sequence of die attach process. </LI> <LI> The performance of the GA based BIP is compared with those of other 10 different robot arm operation methods utilizing simulation. </LI> <LI> It is found that the proposed GA based on BIP provides more efficient PAP sequence than other methods in total transfer distance point of view. </LI> <LI> It is proved that PAP sequences from both conventional robot arm movements and circular movements (CMs) are not optimal. </LI> </UL> </P> <P><B>Graphical abstract</B></P> <P>[DISPLAY OMISSION]</P>

반도체 공정에서의 APC 기법 및 이상감지 및 분류 시스템

하대근(Dae-Geun Ha),구준모(Jun-Mo Koo),박담대(Dam-Dae Park),한종훈(Chong-Hun Han) 제어로봇시스템학회 2015 제어·로봇·시스템학회 논문지 Vol.21 No.4

Traditional semiconductor process control has been performed through statistical process control techniques in a constant process-recipe conditions. However, the complexity of the interior of the etching apparatus plasma physics, quantitative modeling of process conditions due to the many difficult features constraints apply simple SISO control scheme. The introduction of the Advanced Process Control (APC) as a way to overcome the limits has been using the APC process control methodology run-to-run, wafer-to-wafer, or the yield of the semiconductor manufacturing process to the real-time process control, performance, it is possible to improve production. In addition, it is possible to establish a hierarchical structure of the process control made by the process control unit and associated algorithms and etching apparatus, the process unit, the overall process. In this study, the research focused on the methodology and monitoring improvements in performance needed to consider the process management of future developments in the semiconductor manufacturing process in accordance with the age of the APC analysis in real applications of the semiconductor manufacturing process and process fault diagnosis and control techniques in progress.

반도체 공정에서의 APC 기법 및 이상감지 및 분류 시스템

하대근,구준모,박담대,한종훈,Ha, Dae-Geun,Koo, Jun-Mo,Park, Dam-Dae,Han, Chong-Hun 제어로봇시스템학회 2015 제어·로봇·시스템학회 논문지 Vol.21 No.9

Traditional semiconductor process control has been performed through statistical process control techniques in a constant process-recipe conditions. However, the complexity of the interior of the etching apparatus plasma physics, quantitative modeling of process conditions due to the many difficult features constraints apply simple SISO control scheme. The introduction of the Advanced Process Control (APC) as a way to overcome the limits has been using the APC process control methodology run-to-run, wafer-to-wafer, or the yield of the semiconductor manufacturing process to the real-time process control, performance, it is possible to improve production. In addition, it is possible to establish a hierarchical structure of the process control made by the process control unit and associated algorithms and etching apparatus, the process unit, the overall process. In this study, the research focused on the methodology and monitoring improvements in performance needed to consider the process management of future developments in the semiconductor manufacturing process in accordance with the age of the APC analysis in real applications of the semiconductor manufacturing process and process fault diagnosis and control techniques in progress.

In-situ Process Monitoring Data from 30-Paired Oxide-Nitride Dielectric Stack Deposition for 3D-NAND Memory Fabrication

홍상진,김민호,박현근 한국반도체디스플레이기술학회 2023 반도체디스플레이기술학회지 Vol.22 No.4

The storage capacity of 3D-NAND flash memory has been enhanced by the multi-layer dielectrics. The deposition process has become more challenging due to the tight process margin and the demand for accurate process control. To reduce product costs and ensure successful processes, process diagnosis techniques incorporating artificial intelligence (AI) have been adopted in semiconductor manufacturing. Recently there is a growing interest in process diagnosis, and numerous studies have been conducted in this field. For higher model accuracy, various process and sensor data are required, such as optical emission spectroscopy (OES), quadrupole mass spectrometer (QMS), and equipment control state. Among them, OES is usually used for plasma diagnostic. However, OES data can be distorted by viewport contamination, leading to misunderstandings in plasma diagnosis. This issue is particularly emphasized in multi-dielectric deposition processes, such as oxide and nitride (ON) stack. Thus, it is crucial to understand the potential misunderstandings related to OES data distortion due to viewport contamination. This paper explores the potential for misunderstanding OES data due to data distortion in the ON stack process. It suggests the possibility of excessively evaluating process drift through comparisons with a QMS. This understanding can be utilized to develop diagnostic models and identify the effects of viewport contamination in ON stack processes.

단일 클래스 분류기법을 이용한 반도체 공정 주기 신호의 이상분류

조민영,백준걸 대한산업공학회 2012 산업공학 Vol.25 No.2

Process control is essential to operate the semiconductor process efficiently. This paper consider fault classification of semiconductor based cyclic signal for process control. In general, process signal usually take the different pattern depending on some different cause of fault. If faults can be classified by cause of faults, it could improve the process control through a definite and rapid diagnosis. One of the most important thing is a finding definite diagnosis in fault classification, even-though it is classified several times. This paper proposes the method that one-class classifier classify fault causes as each classes. Hotelling T2 chart, kNNDD(k-Nearest Neighbor Data Description), Distance based Novelty Detection are used to perform the one-class classifier. PCA(Principal Component Analysis) is also used to reduce the data dimension because the length of process signal is too long generally. In experiment, it generates the data based real signal patterns from semiconductor process. The objective of this experiment is to compare between the proposed method and SVM(Support Vector Machine). Most of the experiments' results show that proposed method using Distance based Novelty Detection has a good performance in classification and diagnosis problems.

Volatile and Nonvolatile Memory Devices for Neuromorphic and Processing-in-memory Applications

Seongjae Cho 대한전자공학회 2022 Journal of semiconductor technology and science Vol.22 No.1

The motivation for driving semiconductor devices can be found in the development of advanced computers which can contribute to the betterment in our daily lives. The contribution has been largely made by semiconductor logic devices traveling the pavements identified as technology nodes for device shrinkage that enables high-speed and low-power operations. Lighter and faster processors are the everlasting goals in electronics and computer science, and have been concerned with logic technologies. However, the vast amount of data that should be dealt are consistently requiring an innovative way out of the conventional serial data communication and processing. Data need to be processed in a shorter time but the irreducibilities in logic switching time, data propagation time in metallic interconnection accompanying RC delay, and the time amount spent in the serial communication between logic and memory units should be quenched. It is quite hard to control the former two factors which are largely determined by physical limits and fabrication technology ones in recent days but the latter still has room for reduction by novel devices and architectures specifically designed for maximizing the parallelism in data processing and communication. The semiconductor memories let aside the advancements in processor technologies now is being moved to the center of renovation toward the future computers in the ultimate architecture. In this review, the roles and requirements of semiconductor memories for memory-oriented processors are investigated in the highlights of applications in the neuromorphic system and processing-in-memory (PIM) architectures.

반도체공정 이상탐지 및 클러스터링을 위한 심볼릭 표현법의 적용

노웅기(Woong-Kee Loh),홍상진(Sang Jeen Hong) 한국정보과학회 2009 정보과학회 컴퓨팅의 실제 논문지 Vol.15 No.11

반도체(semiconductor) 기술은 1950년대에 집적 회로(integrated circuit, IC)가 발명된 이후 오늘날까지 급속한 발전을 거듭하고 있다. 하나의 완전한 반도체를 제조하기 위해서는 매우 다양하고 긴공정을 거쳐야 한다. 반도체 제조 생산성을 높이기 위하여 공정들이 종료되기 전에 미리 이상(fault)을 발견하기 위한 이상탐지 및 분류(fault detection and classification, FOC)에 대한 많은 연구가 진행되고 있다. 이를 위하여 다양한 반도체 장비에 갖가지 종류의 센서를 부착하여 일정한 시간 간격으로 원하는 값을 측정한다. 이러한 측정 값은 실수 값들의 연속이므로 시계열(time- seIies) 데이터의 일종이다. 본 논문에서는 반도체 공정에서의 이상탐지 및 클러스터링을 수행하는 알고리즘을 제안한다. 제안된 알고리즘은 시계열 데이터를 심불릭 표현법(symbolic representation) 으로 변환하여 이상을 탐지하는 기존의 알고리즘을 수정한 것이다. 본 논문의 공헌은 일반적인 시계열 데이터에 대한 기존의 이상탐지 알고리즘을 수정하여 반도체 공정 데이터에 대해서도 활용할 수 있음을 보일 뿐만 아니라, 이상탐지 및 클러스터링의 정확성을 높이는 실험 결과를 제시하는 것이다. 실험 결과, 본 논문에서 제안한 알고리즘은 긍정 오류(false positive) 및 부정 오류(false negative)를 모두 발생하지 않았다. Since the invention of the integrated circuit (IC) in 1950s, semiconductor technology has undergone dramatic development up to these days. A complete semiconductor is manufactured through a diversity of processes. For better semiconductor productivity, fault detection and classification (FDC) has been rigorously studied for finding faults even before the processes are completed. For FDC, various kinds of sensors are attached in many semiconductor manufacturing devices, and sensor values are collected in a periodic manner. The collection of scnsor values consists of sequences of real numbers, and hence is regarded as a kind of time-series data. In this paper, we propose an algorithm for dctecting and clustering faults in semiconductor processes. The proposed algorithm is a modification of the existing anomaly detection algorithm dealing with symbolically-represented time-series. The contributions of this paper are: (1) showing that a modification of the existing anomaly detection algorithm dealing with general time-series could be used for semiconductor process data and (2) presenting experimental results for improving correctness of fault detection and clustering. As a result of our expeliment, the proposed algorithm caused neither false positive nor false negative.

Lot Size 와 이송단위 변경을 통한 반도체 패키징 공정 WIP 감소 사례

박희남(Hee N. Park),박상철(Sang C. Park) (사)한국CDE학회 2016 한국 CAD/CAM 학회 학술발표회 논문집 Vol.2016 No.동계

This paper is case study on reduction of WIP and lead time of semiconductor packaging process. Now days the importance of packaging process in semiconductor is growing. Because more than 50% of the electrical signal delay caused by the package delay. Reducing WIP and lead time in manufacturing processes and critical issues. WIP and lead time of the semiconductor process is especially important because release of a new product cycle is short and high processing difficulty. So we change lot size and transfer unit for reduction of WIP and lead time for improve the packaging process. The main objective of this paper is to analyze the effect between lot size, transfer unit, WIP and lead time with simulation of different scenarios.

The pH-dependent corrosion behavior of ternary oxide semiconductors and common metals and its application for solution-processed oxide thin film transistors circuit integration

Cho, Sung Woon,Kim, Young Been,Kim, Da Eun,Kim, Kyung Su,Yoon, Young Dae,Kang, Won Jun,Lee, Woobin,Cho, Hyung Koun,Kim, Young Hun Elsevier 2017 Journal of alloys and compounds Vol.714 No.-

<P><B>Abstract</B></P> <P>Individual oxide semiconductors and metals experience unique pH-dependent phase-transition into natively stable phases (metal, metal ions, or oxide phases) in various acidic and basic solutions. Thus, the corrosion behavior of oxide semiconductors and metals can be engineered by controlling pH values. In particular, the specific pH value induced interesting corrosion behavior that oxide semiconductor becomes chemically-stable and metal solely experiences active ionization. First, the pH-dependent corrosion behavior of ternary oxide semiconductors [ZnSnO (ZTO) and InZnO (IZO)] and common metals (Mo and Mo/Cu) was explored based on theoretical Pourbaix diagram and experimental corrosion data. Next, the pH-dependent corrosion behavior based back-channel wet-etch (BCWE) process using pH-controlled wet etchants was designed and applied for chemical damage-, metal residue-, and curing treatment-free solution-processed oxide thin film transistors (TFTs) circuit integration without electrical degradation. Thick-Mo and thin-Mo/thick-Cu could be completely ionized without any metal oxide residues in middle-basic (pH ≥ 10) and weak-acidic (pH = 6) wet-etchants, respectively. Chemically durable ZTO in the broad pH region (6 ≤ pH ≤ 11) indicated sufficient potential as channel candidates for the circuit integration of chemical damage-free oxide TFTs as opposed to IZO (pH = 10). Finally, solution-processed ZTO TFTs could be fabricated with wet-etched Mo and Mo/Cu using the customized wet-etchant condition (pH = 10 and 6) without electrical degradation (current-drop, hump phenomena, or instability) that was inevitably generated in a conventional BCWE.</P> <P><B>Highlights</B></P> <P> <UL> <LI> The ternary zinc tin oxide and indium zinc oxide were synthesized via sol-gel process. </LI> <LI> The pH-dependent corrosion behavior of ternary oxides and common metals was examined. </LI> <LI> Oxide film became stable and metal electrode was solely ionized in specific pH value. </LI> <LI> The pH-dependent corrosion behavior based back-channel wet-etch (BCWE) process was developed. </LI> <LI> The developed BCWE process were applied for solution-processed oxide TFTs integration. </LI> </UL> </P>

반도체 기업들의 초기국제화 배경과 국제화 과정에 대한 비교사례 연구: 대만, 미국, 한국과 일본반도체 기업을 중심으로

권영화 한국전문경영인학회 2015 專門經營人硏究 Vol.18 No.3

As Taiwan, America, Korea and Japan are major countries when it comes to semiconductor industry. So This study aims to analyze the early internationalization and internationalization process of each company in those countries. Also, This study is designed to find out how these companies’ early internationalization and internationalization process are different one another. So This study selected the major company in each country such as TSMC, Qualcomm, Samsung semiconductor and Toshiba semiconductor. Also, This study indicates that TSMC started to export the foundry product to the U.S for the first time, and they felt the need to respond the customer request more actively, so they launched a joint venture in the U.S., and changed it to a wholly owned subsidiary later. And Qualcomm was internationalized by searching for new Asian markets for CDMA instead of the U.S. market because TDMA technology was already widely spreaded out in the U.S. and the EU, and they launched the wholly owned subsidiaries in Asian markets soon. Also, Samsung semiconductor started internationalization by launching a wholly owned subsidiary in the U.S. to acquire advanced technology in the U.S. Lastly Toshiba semiconductor was internationalized for low labor cost by setting up a joint investment company in Malaysia, and they changed it to a wholly owned subsidiary later. In conclusion, this study showed that there are differences in early internationalization and international process according to internal & external environment such as business style and country. Accordingly, there are some implications which could be helpful to other new semiconductor companies.