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Design and verification of high performance digital audio processor
Changwon Ryu,Donghoon Lee,Huajun Chi,Taehoon Kim,Koonshik Cho,Jusung Park 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
This paper describes the design and verification process of a DSP, which is optimized for audio signal processing. We have run 5 audio algorithms on a sixteen-bit fixed-point DSP, TMS320C542, to investigate the usage of each instruction. We then chose the instruction sets that are used in implementing those algorithms. We can obtain more than 100 instructions from TMS320C542's instructions based on that analysis. We have analyzed 3 conventional DSP to get an idea for the architecture design of the target DSP. The designed DSP has 6 level pipelines, double block repeaters to reduce the code size of the multiple loops program, 56bit ALU/accumulator, 25×25bit parallel multiplier, internal memory blocks, and buses that consist of 4 address buses, 6 data buses, 1 program bus, and 3 data buses. The DSP has a data size of 24 bits to support high quality audio, and has 124 instructions and a complexity of 87,350 gates. The designed DSP was verified by a simulation with simple test vectors in the first phase, and was implemented in FPGA to accurately check the function with various test vectors. The test vectors consist of a single instruction test, combination test of instructions, and audio applications (ADPCM, AAC-decoder, MP3- decoder). Finally, we compared the performance of 2 DSPs, 16-bit and 24-bit, in regard to the calculation cycles for many algorithms.
류명걸(Myungkeol Ryu),최택진(Taekjin Choi),김동수(Dongsoo Kim),이문식(Moonsig Lee),김태훈(Taehoon Kim) 한국자동차공학회 2011 한국자동차공학회 부문종합 학술대회 Vol.2011 No.5
The target of developing engine get to improve the fuel economy and performance. An engine intake manifold is optimized by plenum shape, primary and secondary length, port diameter, mass flow rate in the cylinder chamber, etc. Intake manifold also has safety factor for PCV icing and distribution. If the icing is occurred in vehicle, it may give rise to serious accident caused by trouble of break booster, reduction of speed, etc. It becomes more and more important for base intake manifold distribution. AFIM(Air Fuel Imbalance Monitor) function is expected to be implemented in the year 2014 OBDII. Intake manifold imbalance is due to manifold leak, fuel injector trouble, cam position trouble, etc. This paper describes how to check the PCV icing at vehicle and distribution at engine dynamometer and how to improve PCV icing problem.
Design and verification of On-Chip Debug Unit for 32bit RISC core
Hyeongbae Park,Kyungchol Huh,Taehoon Kim,Changwon Ryu,Seungpyo Jung,Jusung Park 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
This paper introduces the basic concept of processor debug and the design and verification procedure of OCDU ( On-Chip Debug Unit), which is designed for 32 bit RISC processor, ARM7 core. OCDU consists of TAP(Test Access Port) that generates the control signals for debugging logic, ICE(In Circuit Emulator) monitoring the operation of the processor, and 3 scan chains. After OCDU and ARM7 core are merged to one designed and implemented with FPGA, the verification of the design is carried out through device recognition, carrying-out instructions of JTAG(Joint Test Action Group), reading and writing the internal registers of the processor and memory, and checking the emulation functions such as setting breakpoints and watch points.
Design and implementaion of the processor for fixed 16-bit data
Donghoon Lee,Changwon Ryu,Taehoon Kim,Kyunsoo Kwon,Wontae Choi,Jusung Park 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
This paper deals with the design and implementation of the 16-bit fixed point pipelined DSP (Digital Signal Processor). The designed DSP has 211 instructions, 6 level pipelines, 40-bit ALU, 17-bit X 17-bit parallel multiplier single-cycle MAC operation, 9 addressing modes, 2 address generators, 8 auxiliary registers and 2 auxiliary register arithmetic units, two 40-bit accumulators and internal RAM. The synthesizable RTL code of the DSP is coded with Verilog HDL and has a complexity of 69,860 in two input NAND gates. We verified the function of the DSP by a simulation with a single instruction test as the first step, implemented the DSP with FPGA to accurately check the functions and to reduce the verification time. The test vectors have a single instruction test, combinational test of instructions and algorithm applications (ADPCM vocoder and the MP3 decoder). After FPGA verification, the DSP is fabricated with 0.25um CMOS technology. The fabricated DSP operates well at the 106 ㎒ clock rates, and carries out 3 application algorithms.