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Seonjun Choi,이정수,이승백 한국물리학회 2013 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.63 No.2
In this study, we propose a pi(Φ)-gate structure that improves the performance of vertical gate (VG) NAND flash memory structures. The pi-gate (PG) structure extends the gates along the top and the bottom surfaces of the silicon layer, widening the channel width and resulting in an increased device current. The extended gates also enhance gate coupling with the channel by allowing more of the gate field to interact with the channel, giving lower threshold voltages (20% reduction) and lower subthreshold swings (21% reduction) and greatly enhancing the switching characteristics. Also, a PG width of 18 nm resulted in an increase in the programmed threshold voltage shift of 39% compared to that of the conventional VG-NAND structure. The PG structured VG-NAND may allow a non-volatile memory to be further integrated by giving solutions to the high channel resistance and reduced memory performance issues related to integration in vertical dimensions.
Seonjun Choi,Yun-heub Song 대한전자공학회 2018 Journal of semiconductor technology and science Vol.18 No.6
In this study we proposed the ‘Double-Side-Control-Gate’(DSCG) which solves problems the conventional 3-D vertical NAND flash structure using the added Sub-Side-Control-Gate(SSCG) and segregate charge nitride layer. The proposed DSCG structure was simulated and tested by the sentaurus TCAD(Synopsys. Inc) tool and confirmed the reduction of interference effect. To demonstrate the performance improvement of the proposed architecture, we analyzed cell-to-cell interference in 3- bit multi-cells and made quantitative analysis on the reduction of cell-to-cell interference resulting from the application of DSCG. In the analysis, we compared and estimated benefits expected from the application of DSCG by calculating Cell-to-Cell Distance(CTCD), pass voltage, etc. Lastly, we confirmed the above 90% reduction of the Cell-to- Cell interference using the DSCG structure.