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김홍배,곽계달 淸州大學校 1984 論文集 Vol.17 No.2
To analysis Drain currents of polycrystalline semiconductor thin film transistor (TFT) condsidering the effect of grain boundary condition, new approach will be suggested. And the results of comparing between polycrystalline TFT phenomenon in always smaller the drain currents of polycrystalline semiconductor TFT than those of monocrystalline semiconductor TFT.
Bipolar-mode Static Induced Transistor(SIT) 소자 설계에 관한 연구
손상희,김홍배,박찬석,곽계달 청주대학교 산업과학연구소 1993 産業科學硏究 Vol.11 No.-
BSIT is simulated in two-dimensional and simulation results are compared with those of experimental device. To get the accurate design data of BSIT, device operation, carrier dynamics depending on channel impurity concentration and current flows depending on gate depth are examined through two-dimensional numerical simulation. Also, conductivity modulation effect in saturation-mode is analyzed from the distribution of minority carrier and electric field. Through the above procedure, the design procedure of SIT will be more effective.
A Multi-Point Sense Amplifier and High-Speed Bit-Line Scheme for Embedded SRAM
II-Kwon Chang,Kae-Dal Kwack 한국정보과학회 1998 Journal of Electrical Engineering and Information Vol.3 No.3
This paper describes new sense amplifier with fast sensing delay time of 0.54ns and 32kb CMOS embedded SRAM with 4.67ns access time for a 3-V power supply. It was achieved using the sense amplifier with multiple point sensing scheme and high speed bit-line scheme. The sense amplifier saves 25% of the power dissipation compared with the conventional one while maintaining a very short sensing delay. The SRAM uses 0.5m double-polysilicon and triple-metal CMOS process technology. A die size is 1.78㎜×2.13㎜.
High Speed Graphics SDRAM을 위한 저 전력, 저 노이즈 Data Bus Inversion
곽승욱(Seung-Wook Kwack),곽계달(Kae-Dal Kwack) 대한전자공학회 2009 電子工學會論文誌-SD (Semiconductor and devices) Vol.46 No.7
본 논문은 DRAM에서 DBI (Data Bus Inversion)를 이용한 새로운 방식의 High Speed 아키텍쳐를 설명하고자한다. DBI는 SSO와 LSI와 같은 잘 알려진 문제를 감소시키기 위한 방식중의 하나이다. 본 논문에서는 Analog Majority Voter(AMV), DBI Flag에 의한 GIO 제어회로, 새로운 SSO Algorithm과 같은 많은 아키텍쳐들이 Data Bus의 천이(Toggle) 개수를 줄이기 위해서 제안되었다. DBI Flag에 의해 GIO데이터 반전 여부를 결정되기 때문에 파워 소모가 감소될 수 있고, 데이터 Eye diagram도 40ps이상 증가될 수 있게 되었다. 제안된 DBI Scheme을 이용하였을 때 High speed 동작에서 거의 안정한 SI특성을 얻을 수 있게 됐다. 90nm CMOS TechNoogy를 이용하여 제조되었다. This paper presents new high speed architecture using DBI(Data Bus Inversion) in DRAM. The DBI is one of the general methods in the signaling circuits to decrease the known problems such as SSO and LSI<SUP>[1]</SUP>. Many architectures have been proposed to reduce the number of transitions on the data bus. In this paper, the DBI, the Analog Majority Voter (AMV) circuit, the GIO control circuit and the SSO algorithm are newly proposed. The power consumption can be reduced with the help of direct GIO inversion method and the eye diagram of data can be increased to 40ps. Using proposed DBI scheme can produce almost stable SI of DQs against high speed operation. The DBI is fabricated in 90nm CMOS TechNoogy.
박장우,곽계달,박광민 순천향대학교 1993 논문집 Vol.16 No.3
In this paper, two dimensonal numercial simulations of short channel MOSFETs are performed. The drift-diffusion model as physical model and the control volume formulation method as discretization method are used. To verify the validity of this paper, the calculated I-V characteristics are compared with experimental data. To study short channel effect, MOSFET with gate length of 0.5㎛ is analyzed with two dimensional numerical simulation. The potential distributions, the electron concentration distribution and the hole concentration distributions in MOSFETs are shown with the various applied voltages. Also, to investigate the characteristics of MOSFET with the various gate lengths. MOSFETs with gate length of 0.5㎛,1.3 ㎛, 2.0 ㎛ are simulated, and the potential distributions are shown.
A Multi-Point Sense Amplifier and High-Speed Bit-Line Scheme for Embedded SRAM
Chang, Il-Kwon,Kwack, Kae-Dal The Korean Institute of Electrical Engineers 1998 Journal of Electrical Engineering and Information Vol.3 No.3
This paper describes new sense amplifier with fast sensing delay time of 0.54ns and 32kb CMOS embedded SRAM with 4.67 ns access time for a 3-V power supply. It was achieved using the sense amplifier with multiple point sensing scheme and highs peed bit-line scheme. The sense amplifier saves 25% of the power dissipation compared with the conventional one while maintaining a very short sensing delay. The SRAM uses 0.5m double-polysilicon and triple-metal CMOS process technology. A die size is 1.78${\times}$mm2.13mm.
Changes in the Electric Parameters of Mesoporous Silicon under Adsorption of Plant Viruses
Yu.A. Vashpanov,Kae-Dal Kwack,Han-Sub Yoon,Jung-Young Son 한국물리학회 2009 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.54 No.6
Changes in the electric parameters of porous silicon under adsorption of nematode-transmitted polyhedral-type plant viruses, such as tomato ringspot virus, grapevine virus A and grapevine fan leaf virus, are investigated at room temperature. The pore sizes of the porous silicon are bigger than the characteristic sizes of the plant viruses, which are considered as having a spherical shape. Plant viruses adsorbed on the surface of porous silicon change the voltage-current and the voltage-capacitance characteristics. The changes in these characteristics depend on the nature of the adsorbed virus and are mostly caused by modifications in the characteristics of the potential barriers formed between nanowires which are thought to be composed of mesoporous silicon. The adsorbed biological particles (plant viruses) on the voltage-current characteristic redistribute the potential barriers in accordance with the applied voltage and the nature of the virus.