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완전평형 전류 적분기를 이용한 3V CMOS 연속시간 필터 설계
안정철,유영규,최석우,김동용,윤창훈,An, Jeong-Cheol,Yu, Yeong-Gyu,Choe, Seok-U,Kim, Dong-Yong,Yun, Chang-Hun 대한전자공학회 2000 電子工學會論文誌-SC (System and control) Vol.37 No.4
본 논문에서는 완전평형 전류 적분기를 이용하여 저전압 구동이 가능하고 고주파수 응용이 가능한 연속시간 필터를 설계하였다. 적분기 회로의 평형 구조 특성 때문에 짝수 차수의 고조파 성분들이 제거되고, 입력 신호 범위가 2배가되어 제안된 필터는 개선된 잡음 특성과 넓은 동적범위를 갖는다. 또한 상보형 전류미러를 이용하기 때문에 바이어스 회로가 간단하고 필터의 차단주파수는 단일 바이어스 전류원에 의해 간단히 제어할 수 있다. 설계의 예로 3차 버터워스 저역통과 필터를 개구리도약법으로 구현하였고, 제안된 완전평형 전류모드 필터는 0.65㎛ CMOS n-well 공정 파라미터를 이용하여 SPICE 시뮬레이션한 후 필터의 특성을 검토하였다. 시뮬레이션 결과 3V의 공급 전압에서 50㎒의 차단주파수, 1%의 THD에서 69㏈의 동적 범위를 갖고, 전력소모는 4㎽이다. In this paper, a continuous-time filter for low voltage and high frequency applications using fully-balanced current integrators is presented. As the balanced structure of integrator circuits, the designed filter has improved noise characteristics and wide dynamic range since even-order harmonics are cancelled and the input signal range is doubled. Using complementary current mirrors, bias circuits are simplified and the cutoff frequency of filters can be controlled easily by a single DC bias current. As a design example, the 3rd-order lowpass Butterworth filter with a leapfrog realization is designed. The designed fully-balanced current-mode filter is simulated and examined by SPICE using 0.65${\mu}{\textrm}{m}$ CMOS n-well process parameters. The simulation results show 50MHz cutoff frequency, 69㏈ dynamic range with 1% total harmonic distortion(THD), and 4㎽ power dissipation with a 3V supply voltage.
金炳旭(Byoung-Wook Kim),方駿鎬(Jun-Ho Bang),趙成翊(Seong-Ik Cho),崔碩佑(Seok-Woo Choi),金東龍(Dong-Yong Kim) 대한전기학회 2008 전기학회논문지 P Vol.57 No.3
In this paper, a current-mode integrator for low-voltage, lew-power analog integrated circuits is presented. Using the proposed current-mode integrator, the baseband analog filter is designed for WCDMA wireless communication. To verify the proposed current-mode integrator circuit, Hspice simulation using 1.8V TSMC 0.18㎛ CMOS parameter is performed and achieved 44.9㏈ gain, 15.7㎒ unity gain frequency. The described 3rd-order current-mode baseband analog filter is composed of the proposed current-mode integrator, and SFG(Signal Flow Graph) method is used to realize the baseband filter. The simulated results show 2.12㎒ cutoff frequency which is suitable for WCDMA baseband block.
전류모드 적분기를 이용한 듀얼 모드 기저대역 필터 설계
金炳旭(Byoung-Wook Kim),方駿鎬(Jun-Ho Bang),趙成翊(Seong-Ik Cho),崔碩佑(Seok-Woo Choi),金東龍(Dong-Yong Kim) 대한전기학회 2008 전기학회논문지 P Vol.57 No.3
In this paper, a dual mode baseband analog channel selection filter is described which is designed for the Bluetooth and WCDMA wireless communications. Using the presented current-mode integrator, a dual mode channel selection filter is designed. To verify the current-mode integrator circuit, Hspice simulation using 1.8V Hynix 0.18㎛ standard CMOS technology was performed and achieved 50.0~54.3㏈ gain, 2.29~10.3㎒ unity gain frequency. The described third-order dual mode analog channel selection filter is composed of the current-mode integrator, and used SFG(Signal Flow Graph) method. The simulated results show 0.51, 2.40㎒ cutoff frequency which is suitable for the Bluetooth and WCDMA baseband block each.