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SISD 머신에 부착 가능한 SIMD 벡터 머신의 개념적 설계
조영일,고영웅,Cho Young-Il,Ko Young-Woong 한국정보처리학회 2005 정보처리학회논문지 A Vol.12 No.3
데이터 주소의 계수를 위한 하드웨어 설계가 없는 본 노이만(von Neuman) 개념(SISD)의 컴퓨터에서 데이터의 주소지정은 소프트웨어적으로 수행된다. 그러므로 벡터 데이터 요소들의 주소지정은 인덱싱 기법에 의해 그 요소 수만큼 해당 변수들을 만들어서 사용해야 한다. 이것은 데이터 계수기 없이 명령어 계수기, 즉 PC(program counter)만 하드웨어로 설계되기 때문이다. 본 연구에서는 중앙처리장치 외부에 외형적 구조와 크기를 갖는 단위 벡터의 요소를 액세스하는 하드웨어 유닛의 설계를 제안한다. 벡터 처리는 고속처리가 전제되기 때문에 파이프라인 처리기법(SIMD)으로 설계되어야 한다. 제안한 방법은 시뮬레이션을 통하여 성능 검증을 하였으며, 실험 결과 동일한 프로세싱 유닛을 가지는 벡터 머신 아키텍쳐보다 $12-30\%$ 정도 우수한 성능을 내는 것을 확인하였다. The addressing mode for data is performed by the software in yon Neumann-concept(SISD) computer a priori without hardware design of an address counter for operands. Therefore, in the addressing mode for the vector the corresponding variables as much as the number of the elements should be specified and used also in the software method. This is because not for operand but only for an instructions, quasi PC(program counter) is designed in hardware physically. A vector has a characteristic of a structural dimension. In this paper we propose to design a hardware unit physically external to the CPU for addressing only the elements of a vector unit with the structure and dimension. Because of the high speed performance for a vector processing it should be designed in the SIMD pipeline mechanics. The proposed mechanics is evaluated through a simulation. Our result shows $12\%$ to $30\%$ performance enhancement over CRAY architecture under the same hardware consideration(processing unit).
조영일,Jong-Hyun Park,Chul-Won Lee,라원희,정종욱,Jung-Ro Lee,Kyung-Ho Ma,Seok-Young Lee,Kang-Seob Lee,Myung-Chul Lee,Yong-Jin Park 한국유전학회 2011 Genes & Genomics Vol.33 No.2
Sixteen polymorphic microsatellite (SSR) markers, developed from an SSR-enriched genomic DNA library of sesame (Sesamum indicum L.), were used to assess genetic diversity,phylogenetic relationships, and population structure among 150 sesame accessions collected from 22 countries. A total of 121 alleles were detected among the sesame accessions. The number of detected alleles varied from 2 to 18, with an average of 7.6 alleles per locus. Polymorphism information content values ranged from 0.03 to 0.79, with an average of 0.42. These values indicated an excess of heterozygous individuals at 16 loci and an excess of homozygous individuals at three loci. Of these, 32 genotype-specific alleles were identified at 11 of 16 polymorphic SSR markers. Cluster analyses were performed by accession and population, revealing a complex accession distribution pattern with mean genetic similarity coefficient of 0.45 by accession and 0.52 by population. The wide variation in genetic similarity among the accessions revealed by SSRs reflected a high level of polymorphism at the DNA level. Model-based structure analysis revealed the presence of three groups that were basically consistent with the clustering results based on genetic distance. These findings may be used to augment the sesame germplasm and to increase the effectiveness of sesame breeding.
조영일 水原大學校 2014 論文集 Vol.28 No.-
Modern processors have large on-chip caches to mitigate off-chip memory latency. The Least Recently Used (LRU) replacement policy has been widely adapted in a microprocessor for the past decades. The LRU replacement policy represents the cache blocks in a set as LRU stack. This policy picks the LRU block as the replacement candidate. The LRU replacement policy has several problems. It does not exploit frequency information of cache accesses. And it may experience cache thrashing when access to cache exhibits cyclic patterns and the cache capacity is less than the working set. And it is expensive to implement in hardware. This paper proposes an new replacement policy which exploits both recency and frequency information of a program. A victim block can be chosen from either the bottom or the top block of the queue, which is controlled by hit/miss bit. This paper also propose to divide the blocks in a cache set into groups where each group implements the proposed replacement to resolve the problems of the proposed replacement. The victim block is chosen alternately from the bottom block of each group. The proposed policy reduces the average MPKI of the baseline 1MB 16-way L3 cache by 13.4%, reduces the storage requirement by 44% and simplifies the circuit design compared to LRU.