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柳相大 한국국제경제학회 2002 국제경제연구 Vol.8 No.1
우리나라 외환시장의 리스크 프리미엄은 자유변동환율제도의 도입과 외환자유화 확대에도 불구하고 양(+)의 수준을 지속하고 있어 외환시장의 효율성이 아직은 미흡한 수준인 것으로 나타났다. 이는 주로 우리나라 외환시장의 구조적 특성 등에 따른 것으로 판단된다. 또한 리스크 프리미엄에 대한 주요 변수와의 실증분석에서는 시장개입과 미국의 주가지수가 리스크 프리미엄에 통계적으로 유의한 영향을 미치는 것으로 파악되었다. 이러한 결과는 현재 우리나라의 외환시장에 큰 영향을 미치는 요인이 주로 주식시장을 중심으로 한 외국인의 포트폴리오 자금유출입이라는 사실을 반영하는 것으로 보인다. 기타 변수들의 리스크 프리미엄에 대한 영향력은 통계적으로 유의하지 않은 것으로 나타났다. 이에 따라 향후 우리나라 외환시장규모와 외국환중개회사의 업무기능 등의 확대 및 원화의 국제화 진전 등의 중장기적으로 추진되어 전반적으로 외환시장의 효율성을 제고해 나가는 노력이 필요할 것으로 판단된다. 한편 단기적으로는 급격한 포트폴리오 투자자금 유입, 달러화의 약세나 엔화와의 동조 등에 의한 대외충격으로 환율의 변동이 과도하게 발생하는 경우에는 적절한 시장개입을 통하여 잠재적인 시장위험과 이에 따른 리스트 프리미엄을 줄여나가는 제한적인 노력은 바람직할 것으로 보인다. This paper empirically analyzes the risk premium in the Korean foreign exchange market. The risk premium is consistently large, implying that the Korean FX market is still inefficient even after Korea shifted to a free floating exchange rate system and began opening the domestic market to foreign Investors in late 1997. In the model estimation from daily data, it Is found that the risk premium is significantly influenced by intervention and the stock prices. Other macroeconomic variables, suggested by a two country Inter-temporal asset pricing model, are not found to affect the risk premium.
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유상대,신장규,이용현,이종현 慶北大學校 1983 論文集 Vol.36 No.-
The ion-sensitive field-effect transistor (ISFET) is one of the family of chemically sensitive semiconductor devices(CSSD) which has been the object of considerable research and development. This study describes the operation of an ISFET as an electronic device. The measurement circuit based on this operation theory is developed for an appropriate ISFET application.
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劉尙大 慶北大學校 1990 論文集 Vol.49 No.-
This paper describes a method for the automatic generation of triangular finite elements within any arbitrary multi-connected regions. In this method the elements and nodes are introduced at the same time to improve the computation speed, and the Laplacian mesh smoothing is used to improve the quality of mesh. The mesh density control is provided.
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유상대,이건일,장종국 경북대학교 전자기술연구소 1988 電子技術硏究誌 Vol.9 No.1
Nondestructive measurement of bulk carrier generation lifetime and surface carrier generation velocity is discussed and experimentally determined. The technique is based on the measurement of transverse acoustoelectric voltage(TVA) generated by surface acoustic wave(SAW). The wafers have undergone different chemical etch removal, polish removal and forming gas annealing treatments. Measurement under the applied do bids voltage is performed in order to distinguish between the surface and bulk effects. The TAV amplitude and the transition time dependences on the applied do bias voltage also reveal the surface potential at zero bias and the approximate position of recombination center within the silicon bandgap, respectively.
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A Unified Channel Thermal Noise Model for Short Channel MOS Transistors
유상대 대한전자공학회 2013 Journal of semiconductor technology and science Vol.13 No.3
A unified channel thermal noise modelvalid in all operation regions is presented for shortchannel MOS transistors. It is based on smoothinterpolation between weak and strong inversionmodels and consistent physical model includingvelocity saturation, channel length modulation, andcarrier heating. From testing for noise benchmarkand comparing with published noise data, it is shownthat the proposed noise model could be useful insimulating the MOSFET channel thermal noise in alloperation regions.
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Small-Signal Analysis of a Differential Two-Stage Folded-Cascode CMOS Op Amp
유상대 대한전자공학회 2014 Journal of semiconductor technology and science Vol.14 No.6
Using a simplified high-frequency small-signal equivalent circuit model for BSIM3 MOSFET, the fully differential two-stage folded-cascode CMOS operational amplifier is analyzed to obtain its small-signal voltage transfer function. As a result, the expressions for dc gain, five zero frequencies, five pole frequencies, unity-gain frequency, and phase margin are derived for op amp design using design equations. Then the analysis result is verified through the comparison with Spice simulations of both a high speed op amp and a low power op amp designed for the 0.13 μm CMOS process.
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Design of CMOS Op Amps Using Adaptive Modeling of Transistor Parameters
유상대 대한전자공학회 2012 Journal of semiconductor technology and science Vol.12 No.1
design paradigm using sequential geometric programming is presented to accurately design CMOS op amps with BSIM3. It is based on new adaptive modeling of transistor parameters through the operating point simulation. This has low modeling cost as well as great simplicity and high accuracy. The short-channel dc, high-frequency small-signal, and short-channel noise models are used to characterize the physical behavior of submicron devices. For low-power and low-voltage design, this paradigm is extended to op amps operating in the subthreshold region. Since the biasing and modeling errors are less than 0.25%, the characteristics of the op amps well match simulation results. In addition,small dependency of design results on initial values indicates that a designed op amp may be close to the global optimum. Finally, the design paradigm is illustrated by optimizing CMOS op amps with accurate transfer function.
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유상대 한국센서학회 2001 센서학회지 Vol.10 No.2
Using transmission-line equivalent circuit based on cross-field model for an interdigital acoustic wave transducer, an efficient simulation technique of SAW filters by SPICE is proposed. Propagation of surface acoustic wave is modeled as transmission line so that frequency-dependent circuit elements are not needed in the equivalent circuit of an interdigital transducer. Because the equivalent circuits for frequency-dependent circuit elements are not derived approximately, and a small number of circuit elements are used in the equivalent circuit for filters, simulation time is much reduced. The utility of the proposed technique is demonstrated through simulation for the characteristics of SAW filters such as insertion loss, input admittance, passband ripple, and harmonic frequency response.
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유상대,이주상,주리아 경북대학교 전자기술연구소 2001 電子技術硏究誌 Vol.22 No.2
In this paper, we describe a general method for optimized design of transponder IC circuit for RFID system with 13.56 ㎒ RF signal. We divide the whole circuit into several functional blocks and observe the functional and timing operation. After that, we design the whole transponder IC circuit which is consist of energy storage circuit, monostable multivibrator, BPSK modulator, ROM etc. and simulate them with HSPICE in 0.6 ㎛ CMOS process.
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