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1.57 GHz 대역 GPS를 위한 CMOS RF 수신기 프런트 엔드
남일구 대한전자공학회 2023 전자공학회논문지 Vol.60 No.1
In this paper, a 1.57 GHz RF receiver front-end architecture and circuits are proposed for L1 band GPS receiver applications. The presented RF receiver front-end consists of a low noise amplifier, a two-stage RF polyphase filter, and an I/Q passive down-conversion mixer, an IF transimpedance amplifier, and a two-stage IF polyphase filter. The proposed 1.57 GHz RF receiver front-end is implemented in a 130 nm CMOS process and consumes 3.4 mW at 1.2 V supply voltage. The implemented RF receiver front-end has a conversion gain of 42 dB and a DSB noise figure of 3.8 dB.
남일구,최치훈,이옥구,문현원 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.5
A fully differential RC calibrator for accurate cut-off frequency of a programmable channel selection filter is proposed. The proposed RC calibrator consists of an RC timer, clock generator, synchronous counter, digital comparator, and control block. To verify the proposed RC calibrator, a six-order Chebyshev programmable low-pass filter with adjustable 3 dB cut-off frequency, which is controlled by the proposed RC calibrator, was implemented in a 0.18-m CMOS technology. The channel selection filter with the proposed RC calibrator draws 1.8 mA from a 1.8 V supply voltage and the measured 3 dB cut-off frequencies of the channel selection LPF is controlled accurately by the RC calibrator.
전용철,남일구,최치훈,최준우,문현원 에스케이텔레콤 (주) 2013 Telecommunications Review Vol.23 No.6
본 논문에서는 수중 통신 기술의 동향을 분석하고 이를 수행하기 위하여 수중 통신 기술 관련 특허들을 6종류의 기술분야 및 4종류의 매질로 분류하였다. 수중 통신 기술은 각각의 매질별 특성에 따라 연구개발시 해결과제가 상이하므로, 매질별로 공개된 특허문헌들을 활용하여 연구개발에 참조하는 것이 필요하다. 본 논문에 있어서는 ‘음파, 초음파’, ‘빛’, ‘케이블’및‘전자기파’의 매질별로 주요 특허문헌을 선별하고 매질별로 연구개발 방안을 제안하였다
신현철,남일구,양준모,민병욱,이규호,윤치원,송진호,Hyunchol Shin,Ilku Nam,Jun-Mo Yang,Byung-Wook Min,Kyuho Lee,Chiweon Yoon,Jean Ho Song 반도체공학회 2024 반도체공학회 논문지 Vol.2 No.3
반도체는 전자 기기 및 시스템을 구성하는 핵심 기술로서, 반도체 기술 발전 방향을 예측 및 제시하는 것이 필요하다. 본 연구에서는 무어 법칙에 따른 반도체 소자의 지속적인 집적화 기술, 시스템 응용에 따른 프로세서 기술, 인공지능/기계학습(AI/ML) 지원 프로세서 기술, 외부시스템 연결 기술로서의 광통신 및 무선통신 기술을 중심으로 각 분야의 핵심적인 기술 개발 이슈, 발전 동향, 그리고, 앞으로의 발전 로드맵에 대한 기초적인 연구결과를 제시하였다. Semiconductors are considered as one of the essential technologies in modern electronic devices and systems. Thus, it is required to predict and propose the semiconductor technology development roadmap. This study describes the key semiconductor technology issues, research and development trends, and their future roadmap, in the four areas such as the semiconductor device More-Moore integration technology, system-specific application processor technology, artificial intelligence/machine learning (AI/ML) processor technology, and outside system connectivity via optical and wireless communication.
A UHF CMOS Variable Gain LNA with Wideband Input Impedance Matching and GSM Interoperability
우두형,남일구,이옥구,임동구 대한전자공학회 2017 Journal of semiconductor technology and science Vol.17 No.4
A UHF CMOS variable gain low-noise amplifier (LNA) is designed for mobile digital TV tuners. The proposed LNA adopts a feedback topology to cover a wide frequency range from 474 to 868 MHz, and it supports the notch filter function for the interoperability with the GSM terminal. In order to handle harmonic distortion by strong interferers, the gain of the proposed LNA is step-controlled while keeping almost the same input impedance. The proposed LNA is implemented in a 0.11 m CMOS process and consumes 6 mA at a 1.5 V supply voltage. In the measurement, it shows the power gain of greater than 16 dB, NF of less than 1.7 dB, and IIP3 of greater than -1.7 dBm for the UHF band.
A Folded Cascode CMOS Low Noise Amplifier with Transformer Feedback
김동명,송하선,남일구,임동구 한국전자파학회 2024 Journal of Electromagnetic Engineering and Science Vol.24 No.1
This study proposes a folded cascode CMOS low noise amplifier (LNA) with transformer feedback, implemented using a 0.13-μm CMOS process for wireless local area network front-end module applications. Compared to a conventional cascode inductive source degeneration LNA (ISDLNA), the folded cascode ISDLNA significantly improved the input-referred third-order intercept point (IIP3) as well as the 1-dB compression point (P1dB) by ensuring a large voltage headroom. Furthermore, the designed LNA also achieved a low noise figure (NF), while also saving the silicon area by magnetically coupling the source and folding inductors. When tested experimentally, the proposed LNA showed an S21 of 11.0 dB and an NF of 2.6 dB, while achieving an <i>S</i><sub>11</sub> of -7 dB at the operating frequency of 2.4 GHz. The measured input P1dB and IIP3 were -5.6 dBm and +2.5 dBm, respectively. The power dissipation was 9.6 mW from a 1.2-V supply voltage.