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An Efficient Implementation of LDPC Decoder with Partial Parallel Algorithm for DVB-S2 System
Suksoon Choi1,Minhyuk Kim,Jongtae Bae,Taedoo Park,Namsoo Kim,Jiwon Jung 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
In this paper, we investigate the encoding and decoding method of the irregular LDPC (Low Density Parity Check) codes that offer diverse coding rates from 1/2 to 9/10 defined in the Digital Video Broadcasting (DVB-S2) standard. We study the efficient memory assignment and the implementing method in the LDPC codes.
Hierarchical Transmission Algorithm combined coding method in the T-DMB system
Jongtae Bae,Minhyuk Kim,Suksoon Choi,Taedoo Park,Namsoo Kim,Jiwon Jung 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
T-DMB (Terrestrial Digital Multimedia Broadcasting) system, is based on the Eureka-147 standard, provides various multimedia data services. However TDMB needs more various services and higher throughput while maintaining reception. Therefore, this paper proposes advanced T-DMB system using the unequal error protection system, hierarchical multi level modulation and various coding scheme which is used for recent wireless communication, while maintaining backward compatibility. As the simulation results, proposed advanced T-DMB system has coding gain of 2~6㏈ compared to conventional T-DMB.
An Efficient Design Methodology of Serial Concatenate Coding Scheme for CATV Transmission System
Minhyuk Kim,Jongtae Bae,Suksoon Choi,Taedoo Park,Namsoo Kim,Jiwon Jung 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
This paper describes the design methodology of serial concatenate of extended RS code, trellis coded modulation with 64-/256-QAM, based upon testing and characterization of cable systems. In implementing the cable modem, there are some problems to fabricate and fitting on FPGA chip. First, many clocks are needed in implementing cable modem because of different code rate and different modulation types. To reduce the number of clocks, we use the two memories, which are different clock speed for reading and writing data. Second, this system lost the bit-synchronization and framesynchronization in decoder, the system recognizes that all data is error. This paper solves the problems by using simple 5-stage registers and unique sync-word. Based on solutions for about problems, the cable modem is fabricated on FPGA chip name as Vertex Ⅱ pro xc2vp30-5 by Xilinx, and we confirmed the effectiveness of the results.