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A Charge Trap Folded nand Flash Memory Device With Band-Gap-Engineered Storage Node
Seongjae Cho,Won Bo Shim,Yoon Kim,Jang-Gn Yun,Jong Duk Lee,Hyungcheol Shin,Jong-Ho Lee,Byung-Gook Park IEEE 2011 IEEE transactions on electron devices Vol.58 No.2
<P>A charge trap folded NAND (FNAND) Flash memory device with band-gap-engineered (BE) storage node is proposed. Because of the compact cell layout without junction contacts, a NAND Flash memory is the most suitable memory medium for electronic appliances. Two memory cells are put together to have a common vertical channel, which enables one to achieve a theoretical near-30-nm technology. The resulting array is made by folding the conventional 2-D Flash memory and is called FNAND. The memory storage node uses a BE stack structure, where the oxide-nitride-oxide multilayers replace the tunnel oxide. The fin structures for both wordline and bitline have been formed by sidewall spacer patterning, instead of photolithography. The fabrication processes for SONONOS NAND Flash memory having independent double gates are explained. Electrical characteristics regarding memory operations under paired cell interference are analyzed.</P>
Seongjae Cho,Shinichi O’uchi,Kazuhiko Endo,Sang Wan Kim,Younghwan Son,In Man Kang,Meishoku Masahara,James S. Harris,Byung-Gook Park 대한전자공학회 2010 Journal of semiconductor technology and science Vol.10 No.4
In this work, reliable methodology for device design is presented. Based on this method, the underlap length has been optimized for minimizing the gateinduced drain leakage (GIDL) in a 22-㎚ node 4-terminal (4-T) silicon-on-insulator (SOI) fin-shaped field effect transistor (FinFET) by TCAD simulation. In order to examine the effects of underlap length on GIDL more realistically, doping profile of the source and drain (S/D) junctions, carrier lifetimes, and the parameters for a band-to-band tunneling (BTBT) model have been experimentally extracted from the devices of 90-㎚ channel length as well as pnjunction test element groups (TEGs). It was confirmed that the underlap length should be near 15 ㎚ to suppress GIDL effectively for reliable low standby power (LSTP) operation.
RF Performance and Small-Signal Parameter Extraction of Junctionless Silicon Nanowire MOSFETs
Seongjae Cho,Kyung Rok Kim,Byung-Gook Park,In Man Kang IEEE 2011 IEEE transactions on electron devices Vol.58 No.5
<P>This paper presents a radio-frequency (RF) model and extracted model parameters for junctionless silicon nanowire (JLSNW) metal-oxide-semiconductor field-effect transistors (MOSFETs) using a 3-D device simulator. JLSNW MOSFETs are evaluated for various RF parameters such as cutoff frequency <I>fT</I>, gate input capacitance, distributed channel resistances, transport time delay, and capacitance by the drain-induced barrier lowering effect. Direct comparisons of high-frequency performances and extracted parameters are made with conventional silicon nanowire MOSFETs. A non-quasi-static RF model has been used, along with SPICE to simulate JLSNW MOSFETs with RF parameters extracted from 3-D-simulated <I>Y</I>-parameters. The results show excellent agreements with the 3-D-simulated results up to the high frequency of <I>fT</I>.</P>
Seongjae Cho,Byung-Gook Park IEEE 2011 IEEE transactions on electron devices Vol.58 No.8
<P>In this brief, an advanced sensing scheme for ultrathin-body vertical Flash memory device is introduced experimentally. Without an increment in the number of read operations, the program/erase states of a memory cell can be identified exactly even with the existence of electrical interference between cells having an ultrathin vertical channel in common. The novel sensing scheme, i.e., the double sensing per 2 bits method, was validated for a fabricated device with a channel thickness of 80 nm. The proposed method can be also used as reference for establishing a smart sensing scheme for multilevel cell NAND Flash memory devices.</P>
Seongjae Cho,Il Han Park,Tae Hun Kim,Jung Hoon Lee,Jong Duk Lee,Hyungcheol Shin,Byung-Gook Park 대한전자공학회 2005 Journal of semiconductor technology and science Vol.5 No.3
Recently, a novel multi-bit nonvolatile memory based on double gate (DG) MOSFET is proposed to overcome the short channel effects and to increase the memory density. We need more complex voltage schemes for DG MOSFET devices. In view of peripheral circuits driving memory cells, one should consider various voltage sources used for several operations. It is one of the key issues to minimize the number of voltage sources. This criterion needs more caution in considering a DG nonvolatile memory cell that inevitably requires more number of events for voltage sources. Therefore figuring out the permissible range of operating bias should be preceded for reliable operation. We found that reliable operation largely depends on the depletion conditions of the silicon channel according to charge amount stored in the floating gates and the negative control gate voltages applied for read operation. We used Silvaco Atlas, a 2-D numerical simulation tool as the device simulator.
Seongjae Cho,Jae Sung Lee,Kyung Rok Kim,Byung-Gook Park,Harris, J. S.,In Man Kang IEEE 2011 IEEE transactions on electron devices Vol.58 No.12
<P>The small-signal parameters of gate-all-around tunneling field-effect transistors (GAA TFETs) with different gate lengths were extracted and analyzed in terms of their gate capacitance, source-drain conductance, transconductance, distributed channel resistance, and inversion layer length. Because of the unique current drive and inversion layer formation mechanisms of a TFET compared to a conventional MOSFET, the gate-bias dependence values of the primary small-signal parameters of a GAA TFET also differ. Based on understanding these parameters, the high-frequency performances of GAA TFETs were investigated using a technology computer-aided design simulation. A nonquasistatic radio-frequency model was used to extract the small-signal parameters, which were verified up to 100 GHz. The modeling results showed excellent agreement with the Y-parameters up to the cutoff frequency f<SUB>T</SUB>.</P>