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An Energy-Efficient 64-bit Prefix Adder based on Semidynamic and Bypassing Structures
Hwang, Jaemin,Choi, Seongrim,Nam, Byeong-Gyu The Institute of Electronics and Information Engin 2015 Journal of semiconductor technology and science Vol.15 No.1
An energy-efficient 64-bit prefix adder is proposed for micro-server processors based on both semidynamic and bypassing structures. Prefix adders consist of three main stages i.e. propagate-generate (PG) stage, carry merge (CM) tree, and sum generators. In this architecture, the PG and CM stages consume most of the power because these are based on domino circuits. This letter proposes a semidynamic PG stage for its energy-efficiency. In addition, we adopt the bypassing structure on the CM tree to reduce its switching activity. Experimental results show 19.1% improvement of energy efficiency from prior art.
Efficient Large Dataset Construction using Image Smoothing and Image Size Reduction
Jaemin HWANG,Sac LEE,Hyunwoo LEE,Seyun PARK,Jiyoung LIM 한국인공지능학회 2023 인공지능연구 (KJAI) Vol.11 No.1
With the continuous growth in the amount of data collected and analyzed, deep learning has become increasingly popular for extracting meaningful insights from various fields. However, hardware limitations pose a challenge for achieving meaningful results with limited data. To address this challenge, this paper proposes an algorithm that leverages the characteristics of convolutional neural networks (CNNs) to reduce the size of image datasets by 20% through smoothing and shrinking the size of images using color elements. The proposed algorithm reduces the learning time and, as a result, the computational load on hardware. The experiments conducted in this study show that the proposed method achieves effective learning with similar or slightly higher accuracy than the original dataset while reducing computational and time costs. This color-centric dataset construction method using image smoothing techniques can lead to more efficient learning on CNNs. This method can be applied in various applications, such as image classification and recognition, and can contribute to more efficient and cost-effective deep learning. This paper presents a promising approach to reducing the computational load and time costs associated with deep learning and provides meaningful results with limited data, enabling them to apply deep learning to a broader range of applications.
An Energy-Efficient 64-bit Prefix Adder based on Semidynamic and Bypassing Structures
Jaemin Hwang,Seongrim Choi,Byeong-Gyu Nam 대한전자공학회 2015 Journal of semiconductor technology and science Vol.15 No.1
An energy-efficient 64-bit prefix adder is proposed for micro-server processors based on both semidynamic and bypassing structures. Prefix adders consist of three main stages i.e. propagate-generate (PG) stage, carry merge (CM) tree, and sum generators. In this architecture, the PG and CM stages consume most of the power because these are based on domino circuits. This letter proposes a semidynamic PG stage for its energy-efficiency. In addition, we adopt the bypassing structure on the CM tree to reduce its switching activity. Experimental results show 19.1% improvement of energy efficiency from prior art.
I/O 부하와 데이터 지역성을 고려한 데드라인 기반 맵리듀스 스케쥴링 기법
황재민(Jaemin Hwang),김천중(Cheonjung Kim),오현교(Hyunkyo Oh),임종태(Jongtae Lim),복경수(Kyoungsoo Bok),유재수(Jaesoo Yoo) 한국콘텐츠학회 2014 한국콘텐츠학회논문지 Vol.14 No.12
본 논문에서는 데드라인 내에 잡을 완료시키기 위한 맵리듀스 스케쥴링 기법을 제안한다. 제안하는 기법은 제출된 잡들을 제한시간 내에 처리하기 위해 데이터 지역성 만족 여부를 확인하고 I/O 부하 및 데드라인 만족 여부를 고려한다. I/O 부하가 존재하는 노드에서 잡을 수행할 경우 복제본 노드의 데이터를 활용하여 잡 태스크 처리 속도를 향상시킨다. 또한, 잡 예상 완료 시간이 데드라인을 초과했음에도 가용 노드가 발생하지 않을 경우 데드라인에 여유가 있는 잡의 태스크를 지연시켜 잡의 완료 시간을 단축시킨다. 제안하는 기법의 우수성을 입증하기 위해 기존 연구와 성능 평가를 수행한다. In this paper, we propose a mapreduce scheduling scheme to complete jobs within a deadline. The proposed scheme first checks data locality and considers I/O load and deadline to complete the submitted jobs within a constraint time. When a job is processed in a node with I/O load, the data of replica nodes are utilized to enhance the job processing time. In addition, if avaliable nodes do not exist in spite that the expected completion time of the job is over the deadline, the job with the most deadline is delayed and then the urgent job is executed to reduce the job completion time. To show the efficiency of the proposed method, it is compared with the existing method through performance evaluation.
비x86 플랫폼 상에서의 CUDA 컴퓨팅을 위한 QEMU 및 GPGPU-Sim 기반 시뮬레이션 프레임워크 개발
황재민(Jaemin Hwang),최종욱(Jong-Wook Choi),최성림(Seongrim Choi),남병규(Byeong-Gyu Nam) 한국산업정보학회 2014 한국산업정보학회논문지 Vol.19 No.2
본 논문에서는 QEMU와 GPGPU-Sim에 기반하여 비x86 플랫폼을 위한 CUDA 시뮬레이션 프레임워크를 제안한다. 기존 CPU-GPU 이종 컴퓨팅 시뮬레이터는 x86 CPU 모델만을 지원하거나 CUDA를 지원하지 않는 한계를 가진다. 제안된 시뮬레이터는 이러한 문제를 해결하기 위해 x86을 포함하여 비x86 CPU 모델을 지원 가능한 QEMU와 CUDA를 지원하는 GPU 시뮬레이터인 GPGPU-Sim을 통합하였다. 이를 통해 비x86 기반의 CUDA 컴퓨팅 환경을 시뮬레이션할 수 있도록 하였다. This paper proposes a CUDA simulation framework for non-x86 computing platforms based on QEMU and GPGPU-sim. Previous simulators for heterogeneous computing platforms did not support for non-x86 CPU models or CUDA computing platform. In this work, we combined the QEMU and the GPGPU-Sim to support the non-x86 CPU models and the CUDA platform, respectively. This approach provides a simulation framework for CUDA computing on non-x86 CPU models.