A System Level Network-on-chip Model with MLDesigner

Agarwal, Ankur,Shankar, Rabi,Pandya, A.S.,Lho, Young-Uhg The Korea Institute of Information and Commucation 2008 Journal of information and communication convergen Vol.6 No.2

Multiprocessor architectures and platforms, such as, a multiprocessor system on chip (MPSoC) recently introduced to extend the applicability of the Moore's law, depend upon concurrency and synchronization in both software and hardware to enhance design productivity and system performance. With the rapidly approaching billion transistors era, some of the main problem in deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm will arise from non scalable wire delays, errors in signal integrity and non-synchronized communication. These problems may be addressed by the use of Network on Chip (NOC) architecture for future System-on-Chip (SoC). We have modeled a concurrent architecture for a customizable and scalable NOC in a system level modeling environment using MLDesigner (from MLD Inc.). Varying network loads under various traffic scenarios were applied to obtain realistic performance metrics. We provide the simulation results for latency as a function of the buffer size. We have abstracted the area results for NOC components from its FPGA implementation. Modeled NOC architecture supports three different levels of quality-of-service (QoS).

Low Power Design of the Neuroprocessor

Pandya, A.S.,Agarwal, Ankur,Chae, G.Y. Korean Institute of Intelligent Systems 2004 INTERNATIONAL JOURNAL of FUZZY LOGIC and INTELLIGE Vol.4 No.1

This paper presents the performance analysis for CPL based design of a Low power digital neuroprocessor. We have verified the functionality of the components at the high level using Verilog and carried out the simulations in Silos. The components of the proposed digital neuroprocessor have also been verified at the layout level in LASI. The layouts have then been simulated and analyzed in Winspice for their timing characteristics. The result shows that the proposed digital neuroprocessor consistently consumes less power than other designs of the same function. It can also be seen that the proposed functions have lesser propagation delay and thus higher speed compared to the other designs.

Low Power Design of the Neuroprocessor

A. S. Pandya,Ankur Agarwal,G. Y. Chae 한국지능시스템학회 2004 INTERNATIONAL JOURNAL of FUZZY LOGIC and INTELLIGE Vol.4 No.1

This paper presents the performance analysis for CPL based design of a Low power digital neuroprocessor. We have verified the functionality of the components at the high level using Veri log and carried out the simulations in Silos. The components of the proposed digital neuroprocessor have also been verified at the layout level in LASI. The layouts have then been simulated and analyzed in Winspice for their timing characteristics. The result shows that the proposed digital neuroprocessor consistently consumes less power than other designs of the same function. It can also be seen that the proposed functions have lesser propagation delay and thus higher speed compared to the other designs.

A Deadlock Free Router Design for Network-on-Chip Architecture

노영욱,Agarwal, Ankur,Mustafa, Mehmet,Shiuku, Ravi,Pandya, A.S.,Lho, Young-Ugh 한국정보통신학회 2007 한국정보통신학회논문지 Vol.11 No.4

다중처리기 SoC(MPSoC) 플랫폼은 SoC 설계 분야에 새로운 여러가지 혁신적인 트랜드를 가지고 있다. 급격히 십억 단위의 트랜지스터 집적이 가능한 시대에 게이트 길이가 $60{\sim}90nm$ 범위를 갖는 서브 마스크로 기술에서 주요문제점들은 확장되지 않는 선 지연, 신호 무결성과 비동기화 통신에서의 오류로 인해 발생한다. 이러한 문제점들은 미래의 SoC을 위한 NOC 구조의 사용에 의해 해결될 수 있다. 대부분의 미래 SoC들은 칩 상에서 통신을 위해 네트워크 구조와 패킷 기반 통신 프로토콜을 사용할 것이다. 이 논문은 NOC 구조를 위한 칩 통신에서 교착상태가 발생되지 않는 것을 보장하기 위해 적극적 turn prohibition을 갖는 적응적 wormhole 라우팅에 대해 기술한다. 또한 5개의 전이중, flit-wide 통신 채널을 갖는 간단한 라우팅 구조를 제시한다. 메시지 지연에 대한 시뮬레이션 결과를 나타내고 같은 연결비율에서 운영되는 다른 기술들의 결과와 비교한다. Multiprocessor system on chip (MPSoC) platform has set a new innovative trend for the System on Chip (SoC) design. With the rapidly approaching billion transistors era, some of the main problem in deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm will arise from non scalable wire delays, errors in signal integrity and un-synchronized communication. These problems may be addressed by the use of Network on Chip (NOC) architecture for future SoC. Most future SoCs will use network architecture and a packet based communication protocol for on chip communication. This paper presents an adaptive wormhole routing with proactive turn prohibition to guarantee deadlock free on chip communication for NOC architecture. It shows a simple muting architecture with five full-duplex, flit-wide communication channels. We provide simulation results for message latency and compare results with those of dimension ordered techniques operating at the same link rates.

Concord: A Proactive Lightweight Middleware to Enable Seamless Connectivity in a Pervasive Environment

Sam Hsu,Mahesh Mutha,A.S. Pandya,YoungUhg Lho 한국지능시스템학회 2005 INTERNATIONAL JOURNAL of FUZZY LOGIC and INTELLIGE Vol.5 No.3

One of the major components of any pervasive system is its proactive behavior. Various models have been developed to provide system wide changes which would enable proactive behavior. A major drawback of these approaches is that they do not address the need to make use of existing applications without modifying the applications. To overcome this drawback, a middleware architecture called "Concord" is proposed. Concord is based on a simple model which consists of Lookup Server and Database. The rewards for this simple model are many. First, Concord uses the existing computing infrastructure. Second, Concord standardizes the interfaces for all services and platforms. Third, new services can be added dynamically without any need for reconfiguration. Finally, Concord consists of Database that can maintain and publish the active set of available resources. Thus Concord provides a solid system for integration of various entities to provide seamless connectivity and enable proactive behavior.

Concord: A Proactive Lightweight Middleware to Enable Seamless Connectivity in a Pervasive Environment

Hsu Sam,Mutha Mahesh,Pandya A.S.,Lho Young-Uhg Korean Institute of Intelligent Systems 2005 INTERNATIONAL JOURNAL of FUZZY LOGIC and INTELLIGE Vol.5 No.3

One of the major components of any pervasive system is its proactive behavior. Various models have been developed to provide system wide changes which would enable proactive behavior. A major drawback of these approaches is that they do not address the need to make use of existing applications without modifying the applications. To overcome this drawback, a middleware architecture called 'Concord' is proposed. Concord is based on a simple model which consists of Lookup Server and Database. The rewards for this simple model are many. First, Concord uses the existing computing infrastructure. Second, Concord standardizes the interfaces for all services and platforms. Third, new services can be added dynamically without any need for reconfiguration. Finally, Concord consists of Database that can maintain and publish the active set of available resources. Thus Concord provides a solid system for integration of various entities to provide seamless connectivity and enable proactive behavior.

NOC Architecture Design Methodology

노영욱,Agarwal, Ankur,Pandya, A. S.,Asaduzzaman, Abu,Lho, Young-Uhg 한국정보통신학회 2006 한국정보통신학회논문지 Vol.10 No.1

다중처리기 SoC(System on Chip) 플랫폼은 SoC 설계를 위한 새로운 혁신적인 경향들을 가지고 있다. QoS 인수와 성능 매트릭스는 SoC을 위한 새로운 설계 방법론을 채택하도록 하였다. 이것은 NOC의 하부 통신 백본뿐만 아니라 전체 시스템 구조가 고도로 확장가능하고, 재사용가능하고, 예측가능하면서 가격과 에너지 측면에서 효율적인 플랫폼이 되도록 구체화할 것이다. 우리는 NOC의 통신 백본 구조가 계층화된 것처럼 NOC의 전체 시스템 구조가 자체적으로 7 계층이 되도록 제안한다. 이런 플랫폼은 동기화 문제를 가지는 병행성을 보다 효과적으로 모델화하는 영역에 특수한 문제들을 분리할 수 있다. 그러한 계층 구조에서 계산 모델은 어떤 응용에 자연스러운 병행성과 동기화 문제를 모형 할 수 있는 뼈대를 제공할 것이다. 그러므로 특정 NOC 영역에서 올바른 계산 모델을 사용하는 것은 아주 중요하다. Multiprocessor system on chip (MPSoC) platforms has set a new innovative trend for the SoC design. Quality of service parameters and performance matrix are leading to the adoption of new design methodology for SoC, which will incorporate highly scalable, reusable, predictable, cost and energy efficient platform not only for underlying communication backbone but also for the entire system architecture of NOC. Like the layered architecture for the communication backbone of NOC, we have proposed the entire system architecture for NOC to be a seven layered architecture in itself. Such a platform can separate the domain specific issues which will model concurrency along with the synchronization issues more effectively. For such a layered architecture, model of computation will provide a framework to that can model concurrency and synchronization issues which are natural for any application. Therefore it becomes extremely important to use a right computation model in a specific NOC region.

Probing charge transport in manganite film through switching parameters

Rathod K.N.,Boricha Hetal,Sagapariya Khushal,Hirpara Bharavi,Dhruv Davit,Joshi A.D.,Pandya D.D.,Singh J.P.,Chae K. H.,Asokan K.,Solanki P.S.,Shah N.A. 한국물리학회 2021 Current Applied Physics Vol.28 No.-

We have investigated the bipolar resistive switching of Y0.95Ca0.05MnO3 (YCMO) thin film on Si substrate using pulsed laser deposition. Simulation of Mn L3,2 near-edge X-ray absorption fine structure has been executed by CTM4XAS to corroborate the presence of a mixed-valence state of Mn ions and oxygen vacancies. The charge transport in the film is described by the space charge limited mechanism. Murgatroyd and space charge limited mechanism relations are used to calculate the mobility and other switching parameters at high resistance state. With a decrease in the switching layer (near to positively biased electrode) thickness, better resistive switching was observed. This work indicates that the localized switching thickness and temperature strongly affect the resistive switching of the YCMO film.

A Novel Low Power Design of ALU Using Ad Hoc Techniques

Agarwa, Ankur,Pandya, A.S.,Lho, Young-Uhg Korean Institute of Intelligent Systems 2005 INTERNATIONAL JOURNAL of FUZZY LOGIC and INTELLIGE Vol.5 No.2

This paper presents the comparison and performance analysis for CPL and CMOS based designs. We have developed the Verilog-HDL codes for the proposed designs and simulated them using ModelSim for verifying the logical correctness and the timing properties of the proposed designs. The proposed designs are then analyzed at the layout level using LASI. The layouts of the proposed designs are simulated in Winspice for timing and power characteristics. The result shows that the new circuits presented consistently consume less power than the conventional design of the same circuits. It can also be seen that these circuits have the lesser propagation delay and thus higher speed than the conventional designs.

A Novel Low Power Design of ALU Using Ad Hoc Techniques

Ankur Agarwa,A. S. Pandya,YoungUhg Lho 한국지능시스템학회 2005 INTERNATIONAL JOURNAL of FUZZY LOGIC and INTELLIGE Vol.5 No.2

This paper presents the comparison and performance analysis for CPL and CMOS based designs. We have developed the Verilog-HDL codes for the proposed designs and simulated them using ModelSim for verifying the logical correctness and the timing properties of the proposed designs. The proposed designs are then analyzed at the layout level using LASI. The layouts of the proposed designs are simulated in Winspice for timing and power characteristics. The result shows that the new circuits presented consistently consume less power than the conventional design of the same circuits. It can also be seen that these circuits have the lesser propagation delay and thus higher speed than the conventional designs.