Large Impending Paradoxical Embolus: Thrombotic Railroading from Right Ventricle to Left Ventricular Outflow

Ankur Agarwal,Ajitkumar Valaparambil,Krishna Kumar Mohanan Nair,Sivadasanpillai Harikrishnan,Deepanjan Bhattacharya 한국심초음파학회 2021 Journal of Cardiovascular Imaging (J Cardiovasc Im Vol.29 No.3

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Software Complexity and Management for Real-Time Systems

Agarwal Ankur,Pandya A.S.,Lbo Young-Ubg The Korea Institute of Information and Commucation 2006 Journal of information and communication convergen Vol.4 No.1

The discipline of software performance is very broad; it influences all aspects of the software development lifecycle, including architecture, design, deployment, integration, management, evolution and servicing. Thus, the complexity of software is an important aspect of development and maintenance activities. Much research has been dedicated to defining different software measures that capture what software complexity is. In most cases, the description of complexity is given to humans in forms of numbers. These quantitative measures reflect human-seen complexity with different levels of success. Software complexity growth has been recognized to be beyond human control. In this paper, we have focused our discussion on the increasing software complexity and the issue with the problems being faced in managing this complexity. This increasing complexity in turn affects the software productivity, which is declining with increase in its complexity.

A System Level Network-on-chip Model with MLDesigner

Agarwal, Ankur,Shankar, Rabi,Pandya, A.S.,Lho, Young-Uhg The Korea Institute of Information and Commucation 2008 Journal of information and communication convergen Vol.6 No.2

Multiprocessor architectures and platforms, such as, a multiprocessor system on chip (MPSoC) recently introduced to extend the applicability of the Moore's law, depend upon concurrency and synchronization in both software and hardware to enhance design productivity and system performance. With the rapidly approaching billion transistors era, some of the main problem in deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm will arise from non scalable wire delays, errors in signal integrity and non-synchronized communication. These problems may be addressed by the use of Network on Chip (NOC) architecture for future System-on-Chip (SoC). We have modeled a concurrent architecture for a customizable and scalable NOC in a system level modeling environment using MLDesigner (from MLD Inc.). Varying network loads under various traffic scenarios were applied to obtain realistic performance metrics. We provide the simulation results for latency as a function of the buffer size. We have abstracted the area results for NOC components from its FPGA implementation. Modeled NOC architecture supports three different levels of quality-of-service (QoS).

Biometrics for Person Authentification: A Surey

Ankur Agarwal,노영욱,김광백,A. S. Pandya 한국지능정보시스템학회 2005 지능정보연구 Vol.11 No.1

As organizations search for more secure authentication methods for user access, e-commerce, and other security applications, biometrics is gaining increasing attention. Biometrics offers greater security and convenience than traditional methods of personal recognition. In some applications, biometrics can replace or supplement the existing technology. In others, it is the only viable approach. Several biometric methods of identification, including fingerprint, hand geometry, facial, ear, iris, eye, signature and handwriting have been explored and compared in this paper. They all are well suited for the specific application to their domain. This paper briefly identifies and categorizes them in particular domain well suited for their application. Some methods are less intrusive than others. 어떤 조직에서 사용자 접근이나 e-Commerce 또는 다른 보안 응용에서 사용하기 위해 보안이 뛰어난 인증 방법을 찾을 때 생체인식시스템이 최근에 보다 많은 주목을 받고 있다. 생체인식시스템은 개인 인식에서 전통적인 방법보다 뛰어난 보안성과 편리성을 제공한다. 생체인식시스템은 어떤 응용 분야에서는 기존의 기술을 대체하거나 보조하고, 다른 응용 분야에서는 사용할 수 있는 유일한 접근방법이 되고 있다. 본 논문에서는 지문, 손 모양, 얼굴, 귀, 홍채, 서명과 필적을 포함한 여러 생체인식 방법들을 조사하고 비교하였다. 이들 방법들은 특정 응용 분야에서 매우 적합하다. 본 논문에서는 특정 응용 분야에 적합한 생체 인식 방법들을 찾아서 분류하였으며, 어떤 방법은 다른 방법에 비해 침입하기가 어려운 것으로 나타났다.

A young man with acute respiratory distress syndrome: eosinophilia is not always “benign”

Ankur Jain,Pankaj Malhotra,Vikas Suri,Ritesh Agarwal,Amanjit Bal,Subhash Varma 대한혈액학회 2017 Blood Research Vol.51 No.4

A young man with acute respiratory distress syndrome: eosinophilia is not always “benign”

Ankur Jain,Pankaj Malhotra,Vikas Suri,Ritesh Agarwal,Amanjit Bal,Subhash Varma 대한혈액학회 2017 Blood Research Vol.52 No.4

Low Power High Frequency Design for Data Transfer for RISC and CISC Architecture

노영욱,Agarwal, Ankur,Pandya, A. S.,Lho, Young-Uhg 한국정보통신학회 2006 한국정보통신학회논문지 Vol.10 No.2

이 논문은 완전설계와 반주문설계 ASIC(Application Specific Integrated Circuit)을 설계 할 때 트랜지스터 수준에서 ad-hoc 기술을 사용한 저전력 고속의 명령어들 설계에 대한 것이다. 제안된 설계는 상위 수준은 Verilog-HDL을 사용하여 검증을 하였고, 논리적 정확성을 화인하기 위하여 ModelSim을 사용하여 시뮬레이션 하였다. 그리고 레이어 수준은 $0.25{\mu}m$ 기술을 사용하는 LASI를 사용하여 시험하였고, Win-spice 시뮬레이션 환경에서 시간 특성을 분석하였다. 시험을 한 결과에 의하면 RISC와 CISC와 같은 범용 프로세서는 전력 소모를 최대 $35\%$까지 감소되었다. 그리고 전파 지연이 많이 감소되었고 CPU의 반입과 수행 사이클의 빈도수가 증가됨에 따라 연산의 전체 빈도수가 증가되었다. This paper presents low power and high frequency design of instructions using ad-hoc techniques at transistor level for full custom and semi-custom ASIC(Application Specific Integrated Circuit) designs. The proposed design has been verified at high level using Verilog-HDL and simulated using ModelSim for the logical correctness. It is then observed at the layout level using LASI using $0.25{\mu}m$ technology and analyzed for timing characteristic under Win-spice simulation environment. The result shows the significant reduction up to $35\%$ in the power consumption by any general purpose processor like RISC or CISC. A significant reduction in the propagation delay is also observed. increasing the frequency for the fetch and execute cycle for the CPU, thus increasing the overall frequency of operation.

A Deadlock Free Router Design for Network-on-Chip Architecture

노영욱,Agarwal, Ankur,Mustafa, Mehmet,Shiuku, Ravi,Pandya, A.S.,Lho, Young-Ugh 한국정보통신학회 2007 한국정보통신학회논문지 Vol.11 No.4

다중처리기 SoC(MPSoC) 플랫폼은 SoC 설계 분야에 새로운 여러가지 혁신적인 트랜드를 가지고 있다. 급격히 십억 단위의 트랜지스터 집적이 가능한 시대에 게이트 길이가 $60{\sim}90nm$ 범위를 갖는 서브 마스크로 기술에서 주요문제점들은 확장되지 않는 선 지연, 신호 무결성과 비동기화 통신에서의 오류로 인해 발생한다. 이러한 문제점들은 미래의 SoC을 위한 NOC 구조의 사용에 의해 해결될 수 있다. 대부분의 미래 SoC들은 칩 상에서 통신을 위해 네트워크 구조와 패킷 기반 통신 프로토콜을 사용할 것이다. 이 논문은 NOC 구조를 위한 칩 통신에서 교착상태가 발생되지 않는 것을 보장하기 위해 적극적 turn prohibition을 갖는 적응적 wormhole 라우팅에 대해 기술한다. 또한 5개의 전이중, flit-wide 통신 채널을 갖는 간단한 라우팅 구조를 제시한다. 메시지 지연에 대한 시뮬레이션 결과를 나타내고 같은 연결비율에서 운영되는 다른 기술들의 결과와 비교한다. Multiprocessor system on chip (MPSoC) platform has set a new innovative trend for the System on Chip (SoC) design. With the rapidly approaching billion transistors era, some of the main problem in deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm will arise from non scalable wire delays, errors in signal integrity and un-synchronized communication. These problems may be addressed by the use of Network on Chip (NOC) architecture for future SoC. Most future SoCs will use network architecture and a packet based communication protocol for on chip communication. This paper presents an adaptive wormhole routing with proactive turn prohibition to guarantee deadlock free on chip communication for NOC architecture. It shows a simple muting architecture with five full-duplex, flit-wide communication channels. We provide simulation results for message latency and compare results with those of dimension ordered techniques operating at the same link rates.

NOC Architecture Design Methodology

노영욱,Agarwal, Ankur,Pandya, A. S.,Asaduzzaman, Abu,Lho, Young-Uhg 한국정보통신학회 2006 한국정보통신학회논문지 Vol.10 No.1

다중처리기 SoC(System on Chip) 플랫폼은 SoC 설계를 위한 새로운 혁신적인 경향들을 가지고 있다. QoS 인수와 성능 매트릭스는 SoC을 위한 새로운 설계 방법론을 채택하도록 하였다. 이것은 NOC의 하부 통신 백본뿐만 아니라 전체 시스템 구조가 고도로 확장가능하고, 재사용가능하고, 예측가능하면서 가격과 에너지 측면에서 효율적인 플랫폼이 되도록 구체화할 것이다. 우리는 NOC의 통신 백본 구조가 계층화된 것처럼 NOC의 전체 시스템 구조가 자체적으로 7 계층이 되도록 제안한다. 이런 플랫폼은 동기화 문제를 가지는 병행성을 보다 효과적으로 모델화하는 영역에 특수한 문제들을 분리할 수 있다. 그러한 계층 구조에서 계산 모델은 어떤 응용에 자연스러운 병행성과 동기화 문제를 모형 할 수 있는 뼈대를 제공할 것이다. 그러므로 특정 NOC 영역에서 올바른 계산 모델을 사용하는 것은 아주 중요하다. Multiprocessor system on chip (MPSoC) platforms has set a new innovative trend for the SoC design. Quality of service parameters and performance matrix are leading to the adoption of new design methodology for SoC, which will incorporate highly scalable, reusable, predictable, cost and energy efficient platform not only for underlying communication backbone but also for the entire system architecture of NOC. Like the layered architecture for the communication backbone of NOC, we have proposed the entire system architecture for NOC to be a seven layered architecture in itself. Such a platform can separate the domain specific issues which will model concurrency along with the synchronization issues more effectively. For such a layered architecture, model of computation will provide a framework to that can model concurrency and synchronization issues which are natural for any application. Therefore it becomes extremely important to use a right computation model in a specific NOC region.

Low Power Design of the Neuroprocessor

Pandya, A.S.,Agarwal, Ankur,Chae, G.Y. Korean Institute of Intelligent Systems 2004 INTERNATIONAL JOURNAL of FUZZY LOGIC and INTELLIGE Vol.4 No.1

This paper presents the performance analysis for CPL based design of a Low power digital neuroprocessor. We have verified the functionality of the components at the high level using Verilog and carried out the simulations in Silos. The components of the proposed digital neuroprocessor have also been verified at the layout level in LASI. The layouts have then been simulated and analyzed in Winspice for their timing characteristics. The result shows that the proposed digital neuroprocessor consistently consumes less power than other designs of the same function. It can also be seen that the proposed functions have lesser propagation delay and thus higher speed compared to the other designs.