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A Novel Low Power Design of ALU Using Ad Hoc Techniques
Agarwa, Ankur,Pandya, A.S.,Lho, Young-Uhg Korean Institute of Intelligent Systems 2005 INTERNATIONAL JOURNAL of FUZZY LOGIC and INTELLIGE Vol.5 No.2
This paper presents the comparison and performance analysis for CPL and CMOS based designs. We have developed the Verilog-HDL codes for the proposed designs and simulated them using ModelSim for verifying the logical correctness and the timing properties of the proposed designs. The proposed designs are then analyzed at the layout level using LASI. The layouts of the proposed designs are simulated in Winspice for timing and power characteristics. The result shows that the new circuits presented consistently consume less power than the conventional design of the same circuits. It can also be seen that these circuits have the lesser propagation delay and thus higher speed than the conventional designs.
A Novel Low Power Design of ALU Using Ad Hoc Techniques
Ankur Agarwa,A. S. Pandya,YoungUhg Lho 한국지능시스템학회 2005 INTERNATIONAL JOURNAL of FUZZY LOGIC and INTELLIGE Vol.5 No.2
This paper presents the comparison and performance analysis for CPL and CMOS based designs. We have developed the Verilog-HDL codes for the proposed designs and simulated them using ModelSim for verifying the logical correctness and the timing properties of the proposed designs. The proposed designs are then analyzed at the layout level using LASI. The layouts of the proposed designs are simulated in Winspice for timing and power characteristics. The result shows that the new circuits presented consistently consume less power than the conventional design of the same circuits. It can also be seen that these circuits have the lesser propagation delay and thus higher speed than the conventional designs.