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傳達 GATE 組合論理를 利用한 8-bit COMS DAC回路의 設計
黃泰善,鄭康敏 成均館大學校 科學技術硏究所 1994 論文集 Vol.45 No.2
This paper describes a 100MHz 8 - b CMOS D/A converter with a current output. To guarantee a low glitch energy, a decorder using transmission function theory and a deglicthing circuit are presented. An integral linearity error caused by error distributions of current sources is reduced by a symmetrical switching. The simulation results show that the maximum conversion rate is 135MHz and the integral errors are less than 0.5LSB. The maximum glitch energy is lOpV.s. The entire circuit dissipates 63.8mW at a 100MHz conversion rate while operating from a single 5V power supply. The circuit is simulated in a 1.2㎛ CMOS process.