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DigiCipher 등하시스템의 하드웨어 구현방법에 관한 연구
채승수,반성범,이기헌,박래홍,김영상,이병욱 대한전자공학회 1996 전자공학회논문지-B Vol.b33 No.6
In this paper, we present the modified CMA (constant modulus algorithm) and LMS (least mean square) algorithms for digiCipher system with reduced hardware cost, in which the pipelined architecture is employed. They yield the performance comparable to that using floating-point operations. We show the effecstiveness of the proposed architecture through the implementation results using VHDL.
채승수,박래홍 대한전자공학회 1995 전자공학회논문지-B Vol.b32 No.10
In this paper, we describe hardware implementation of VSB (Vestigial SideBand) mo-dulation equalization systems for HDTV (High Definition TeleVision). By modifying an adaptive equalization algorithm, we propose a hardware architecture with a low hardware cost and the performance close to floating-point operations. We also employ the pipeline concept to reduce the hardware cost. The effectiveness of the proposed hardware architecture is de- monstrated through computer simulation and the optimization result of VHDL circuit descriptions.
Si Cathode 개발을 위한 연삭 및 폴리싱 가공특성
채승수(Seung-Su Chae),이충석(Choong-Seok Lee),김택수(Taeck-Su Kim),이상민(Sang-Min Lee),허찬(Chan Huh),이종찬(Jong-Chan Lee) 한국기계가공학회 2010 한국기계가공학회지 Vol.9 No.2
This paper reports some experimental result in grinding and polishing of silicon cathodes used in semiconductor manufacturing process. Cup shape diamond core wheels were used in experiments and the radial and tangential grinding forces were measured with surface roughness. In polishing experiments, flat type and donut type wool polishing tools were tested. The experimental results indicate that the grinding forces are proportional to the material removal rates and the surface roughness are inversely proportional to the spindle speed. The surface roughness of polished Si decreases with polishing time and higher spindle speed.
채승수(Seung-Su Chae),이상민(Sang-Min Lee),박휘근(Hwi-Keun Park),조준현(Jun-Hyun Cho),이종찬(Jong-Chan Lee),허찬(Chan Heo) 한국기계가공학회 2013 한국기계가공학회지 Vol.12 No.2
Cathode is an essential component used in plasma etching process which is to make micro pattern on the silicon wafer. The currently used cathodes produce particles at the high temperature plasma etching process. To overcome this problem, a ‘Silicon Only Cathode’ was developed. This ‘Silicon Only Cathode’ requires manufacturing process changes due to the change of shapes, material features, and machining characteristics of work materials. This research investigates the small hole drilling process. The conclusion is that PCD drills with twist angles of 20? and 25? were tested for small hole drilling and the experimental results indicate that the drill with 25? twist angle drill causes less thrust force.
거상투영을 이용한 2단계 고속 블록정합 알고리즘의 하드웨어 설계
판성범,채승수,김준식,박래홍,조위덕,임신일 대한전자공학회 1994 전자공학회논문지-B Vol.b31 No.7
In this paper we investigate the hardware implementation of block matching algorithms (BMAs) for moving sequences. Using systolic arrays we propose a hardware architecture of a two-stage BMA using integral projections which reduces greatly computational complexity with its performance comparable to that of the full search (FS). Proposed hardware architecture is faster than hardware architecture of the FS by 2~15 times. For realization of the FS and two stage BMA modeling and simulation results using SPW and VHDL are also shown.