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차세대 웨어러블 전자시스템용 실리콘 나노선 트랜지스터 연구
임경민,김민석,김윤중,임두혁,김상식,Im, Kyeungmin,Kim, Minsuk,Kim, Yoonjoong,Lim, Doohyeok,Kim, Sangsig 한국진공학회 2016 진공 이야기 Vol.3 No.3
In future wearable electronic systems, 3-dimensional (3D) devices have attracted much attention due to their high density integration and low-power functionality. Among 3D devices, gate-all-around (GAA) nanowire transistor provides superior gate controllability, resulting in suppressing short channel effect and other drawbacks in 2D metal-oxide-semiconductor field-effect transistor (MOSFET). Silicon nanowires (SiNWs) are the most promising building block for GAA structure device due to their compatibility with the current Si-based ultra large scale integration (ULSI) technology. Moreover, the theoretical limit for subthreshold swing (SS) of MOSFET is 60 mV/dec at room temperature, which causes the increase in Ioff current. To overcome theoretical limit for the SS, it is crucial that research into new types of device concepts should be performed. In our present studies, we have experimentally demonstrated feedback FET (FBFET) and tunnel FET (TFET) with sub-60 mV/dec based on SiNWs. Also, we fabricated SiNW based complementary TFET (c-TFET) and SiNW complementary metal-oxide-semiconductor (CMOS) inverter. Our research demonstrates the promising potential of SiNW electronic devices for future wearable electronic systems.
Gate Overlap에 따른 나노선 CMOS Inverter 특성 연구
유제욱(Jeuk Yoo),김윤중(Yoonjoong Kim),임두혁(Doohyeok Lim),김상식(Sangsig Kim) 대한전기학회 2017 전기학회논문지 Vol.66 No.10
In this study, we investigate the influence of an overlap between the gate and source/drain regions of silicon nanowire (SiNW) CMOS (complementary metal-oxide-semiconductor) inverter on bendable plastic substrates and describe their electrical characteristics. The combination of n-channel silicon nanowire field-effect transistor (n-SiNWFET) and p-channel silicon nanowire field-effect transistor (p-SiNWFET) operates as an inverter logic gate. The gains with a drain voltage (Vdd) of 1 V are 3.07 and 1.21 for overlapped device and non-overlapped device, respectively. The superior electrical characteristics of each of the SiNW transistors including steep subthreshold slopes and the high Ion/Ioff ratios are major factors that enable the excellent operation of the logic gate.