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Gate Overlap에 따른 나노선 CMOS Inverter 특성 연구
유제욱(Jeuk Yoo),김윤중(Yoonjoong Kim),임두혁(Doohyeok Lim),김상식(Sangsig Kim) 대한전기학회 2017 전기학회논문지 Vol.66 No.10
In this study, we investigate the influence of an overlap between the gate and source/drain regions of silicon nanowire (SiNW) CMOS (complementary metal-oxide-semiconductor) inverter on bendable plastic substrates and describe their electrical characteristics. The combination of n-channel silicon nanowire field-effect transistor (n-SiNWFET) and p-channel silicon nanowire field-effect transistor (p-SiNWFET) operates as an inverter logic gate. The gains with a drain voltage (Vdd) of 1 V are 3.07 and 1.21 for overlapped device and non-overlapped device, respectively. The superior electrical characteristics of each of the SiNW transistors including steep subthreshold slopes and the high Ion/Ioff ratios are major factors that enable the excellent operation of the logic gate.