40MHz의 대역폭과 개선된 선형성을 가지는 Active-RC Channel Selection Filter

이한열,황유정,장영찬,Lee, Han-Yeol,Hwang, Yu-Jeong,Jang, Young-Chan 한국정보통신학회 2013 한국정보통신학회논문지 Vol.17 No.10

본 논문에서는 40MHz의 대역폭과 개선된 선형성을 가지는 active-RC channel selection filter (CSF)가 제안된다. 제안되는 CSF는 5차 butterworth 필터로써 한 단의 1차 low pass 필터와 두 단의 biquad 기반의 2차 low pass 필터, 그리고 DC offset 제거를 위한 DC 피드백 회로로 구성된다. CSF의 선형성을 개선하기 위해 스위치로 사용되는 MOSFET의 body를 source 노드로 연결한다. 설계된 CSF의 대역폭은 10MHz, 20MHz, 그리고 40MHz로 선택될 수 있으며, 전압 이득은 0dB에서 24dB까지 6dB의 단위로 조정된다. 제안된 CSF는 1.2V 40nm의 1-poly 8-metal CMOS 공정에서 설계된다. 설계된 CSF가 40MHz의 대역폭과 0dB의 gain을 가질 때, OIP3는 31.33dBm이고 in-band ripple은 1.046dB, IRN는 39.81nV/sqrt(Hz)로 시뮬레이션 검증되었다. CSF의 면적과 전력소모는 각각 $450{\times}210{\mu}m^2$와 6.71mW 이다. An active-RC channel selection filter (CSF) with the bandwidth of 40MHz and the improved linearity is proposed in this paper. The proposed CSF is the fifth butterworth filter which consists of a first order low pass filter, two second order low pass filters of a biquad architecture, and DC feedback circuit for cancellation of DC offset. To improve the linearity of the CSF, a body node of a MOSFET for a switch is connected to its source node. The bandwidth of the designed CSF is selected to be 10MHz, 20MHz and 40MHz and its voltage gain is controlled by 6 dB from 0 dB to 24 dB. The proposed CSF is designed by using 40nm 1-poly 8-metal CMOS process with a 1.2V. When the designed CSF operates at the bandwidth of 40 MHz and voltage gain of 0 dB, the simulation results of OIP3, in-band ripple, and IRN are 31.33dBm, 1.046dB, and 39.81nV/sqrt(Hz), respectively. The power consumption and layout area are $450{\times}210{\mu}m^2$ and 6.71mW.

초음파를 이용한 장애물 감지 및 속도조절 전동보드

이한열(Lee Han Yeol),신영훈(Shin Young Hun),최광훈(Choi Gwang Hoon),이상원(Lee Sang Won),이은영(Lee Eun Yeong) 대한기계학회 2018 대한기계학회 춘추학술대회 Vol.2018 No.4

기하학적 불확실성 기반 영상 관성 항법의 원거리 특징점 감지

이한열(Han Yeol Lee),정재형(Jae Hyung Jung),박찬국(Chan Gook Park) 제어로봇시스템학회 2021 제어·로봇·시스템학회 논문지 Vol.27 No.11

In this paper, we propose a new method that classifies the features in a visual-inertial navigation system. The far features provide inaccurate information on the position and velocity of a moving vehicle, and thus, the information provided by the far features should be used for attitude estimation without recovering the feature depths. In contrast, the information obtained from the near features can be used to obtain a reliable depth estimate because of the large parallax in the image plane. However, the criterion for labeling the features as near or far features is ambiguous. Previously, various geometric classification methods based on a stereo camera and measurement uncertainties have been reported. Herein, we present a criterion based on the geometric method using the MSCKF (Multi-State Constraint Kalman filter ). Additionally, we define a new concept — depth uncertainty — as the criterion of feature classification in the MSCKF. Using this criterion, we can draw a limited range defined as the observable region. Implementation of this method can decrease the error caused by the low parallax of the feature. The proposed method is validated through simulations and experiments, showing a 12.7 % and 21.2 % decrease in the mean position error, respectively, using the far features classification.

5.4비트의 유효비트를 가지는 1V 1.6-GS/s 6비트 플래쉬 아날로그-디지털 변환기

이한열(Han-Yeol Lee),정동길(Dong-Gil Jeong),장영찬(Young-Chan Jang) 한국정보기술학회 2013 한국정보기술학회논문지 Vol.11 No.11

This paper proposes A 1V 1.6-GS/s 6-bit flash analog-to-digital converter(ADC). A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation and the dynamic performance of flash ADC is increased by adding a SR latch at the output node of each comparator. The proposed flash ADC is fabricated using a 90nm 1-poly 9-metal CMOS process with 1V supply. The measured DNL(Differential Non-linearity) and INL(Integral Non-linearity) are +0.56/-0.49 LSB(Least Significant Bit) and +0.74/-0.84 LSB, respectively. The measured SNDR(Signal-to-Noise and Distortion Ratio) and ENOB(Effective Number of Bits) are 34.3dB and 5.4 bit for a 800 MHz analog input signal. The ENOB of 0.3 bit was improved by the SR latch added at the output node of each comparator. The power consumption and chip area of flash ADC are 800×500μ㎡ and 399.3mW, respectively.

Reference Driver를 사용한 10비트 10MS/s 축차근사형 아날로그-디지털 변환기

손지수,이한열,김영웅,장영찬,Son, Jisu,Lee, Han-Yeol,Kim, Yeong-Woong,Jang, Young-Chan 한국정보통신학회 2016 한국정보통신학회논문지 Vol.20 No.12

본 논문은 reference driver를 이용한 10비트 10MS/s 축차근사형(SAR: Successive Approximation Register) 아날로그-디지털 변환기(ADC: Analog-to-Digital Converter)를 제안한다. 제안하는 SAR ADC는 커패시터형 디지털-아날로그 변환기(CDAC: Capacitive Digital-to-Analog Converter), 비교기, SAR 로직, 그리고 공급 전압 노이즈에 대한 내성을 향상시키는 reference driver로 구성된다. ${\pm}0.9V$의 아날로그 입력전압을 가지는 SAR ADC를 위해 reference driver는 0.45V, 1.35V의 기준 전압을 생성한다. 설계된 SAR ADC는 $0.18{\mu}m$ CMOS 공정을 이용하여 제작되었으며 1.8V의 공급전압을 사용하였다. 제안된 SAR ADC는 reference driver를 이용하여 +/- 200mV의 공급 전압 변화에서도 ${\pm}0.9V$의 입력 범위를 유지한다. 10MS/s의 샘플링 주파수에서 5.32mW의 전력을 소모한다. 측정된 ENOB는 9.11 비트 이며, DNL과 INL은 각각 +0.60/-0.74 LSB와 +0.69/-0.65 LSB이다. This paper presents a 10 bit successive approximation register (SAR) analog-to-digital converter (ADC) with a reference driver. The proposed SAR ADC consists of a capacitive digital-to-analog converter (CDAC), a comparator, a SAR logic, and a reference driver which improves the immunity to the power supply noise. The reference driver generates the reference voltages of 0.45 V and 1.35 V for the SAR ADC with an input voltage range of ${\pm}0.9V$. The SAR ADC is implemented using a $0.18-{\mu}m$ CMOS technology with a 1.8-V supply. The proposed SAR ADC including the reference driver almost maintains an input voltage range to be ${\pm}0.9V$ although the variation of supply voltage is +/- 200 mV. It consumes 5.32 mW at a sampling rate of 10 MS/s. The measured ENOB, DNL, and INL of the ADC are 9.11 bit, +0.60/-0.74 LSB, and +0.69/-0.65 LSB, respectively.

클록 보정회로를 가진 1V 1.6-GS/s 6-bit Flash ADC

김상훈,홍상근,이한열,박원기,이왕용,이성철,장영찬,Kim, Sang-Hun,Hong, Sang-Geun,Lee, Han-Yeol,Park, Won-Ki,Lee, Wang-Yong,Lee, Sung-Chul,Jang, Young-Chan 한국정보통신학회 2012 한국정보통신학회논문지 Vol.16 No.9

A 1V 1.6-GS/s 6-bit flash analog-to-digital converter (ADC) with a clock calibration circuit is proposed. A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation. Two preamplifier-arrays and each comparator composed of two-stage are implemented for the reduction of analog noises and high speed operation. The clock calibration circuit in the proposed flash ADC improves the dynamic performance of the entire flash ADC by optimizing the duty cycle and phase of the clock. It adjusts the reset and evaluation time of the clock for the comparator by controlling the duty cycle of the clock. The proposed 1.6-GS/s 6-bit flash ADC is fabricated in a 1V 90nm 1-poly 9-metal CMOS process. The measured SNDR is 32.8 dB for a 800 MHz analog input signal. The measured DNL and INL are +0.38/-0.37 LSB, +0.64/-0.64 LSB, respectively. The power consumption and chip area are $800{\times}500{\mu}m2$ and 193.02mW. 클록 보정회로를 가진 1V 1.6-GS/s 6-비트 flash 아날로그-디지털 변환기 (ADC: analog-to-digital converter)가 제안된다. 1V의 저전압에서 고속 동작의 입력단을 위해 bootstrapped 아날로그 스위치를 사용하는 단일 track/hold 회로가 사용되며, 아날로그 노이즈의 감소와 고속의 동작을 위해 평균화 기법이 적용된 두 단의 프리앰프와 두 단의 비교기가 이용된다. 제안하는 flash ADC는 클록 보정회로에 의해 클록 duty cycle과 phase를 최적화함으로 flash ADC의 동적특성을 개선한다. 클록 보정 회로는 비교기를 위한 클록의 duty cycle을 제어하여 evaluation과 reset 시간을 최적화한다. 제안된 1.6-GS/s 6-비트 flash ADC는 1V 90nm의 1-poly 9-metal CMOS 공정에서 제작되었다. Nyquist sampling rate인 800 MHz의 아날로그 입력신호에 대해 측정된 SNDR은 32.8 dB이며, DNL과 INL은 각각 +0.38/-0.37 LSB, +0.64/-0.64 LSB이다. 구현된 flash ADC의 면적과 전력소모는 각각 $800{\times}500{\mu}m2$와 193.02 mW 이다.

IoT 센서를 위한 Majority-voting 기술을 이용하는 200-㎑ 12-bit SAR ADC

황유정(Yu-Jeong Hwang),이한열(Han-Yeol Lee),윤은지(Eunji Youn),정호용(Ho-Young Jeong),장영찬(Young-Chan Jang) 한국통신학회 2019 한국통신학회 학술대회논문집 Vol.2019 No.6

통신 응용을 위한 10 MS/s 13 비트 파이프라인 아날로그-디지털 변환기

정호용(Ho-Young Jeong),이한열(Han-Yeol Lee),장영찬(Young-Chan Jang) 한국통신학회 2019 한국통신학회 학술대회논문집 Vol.2019 No.11

12-비트 10-MS/s CMOS 파이프라인 아날로그-디지털 변환기

조세현(Se-Hyeon Cho),정호용(Ho-yong Jung),도원규(Won-Kyu Do),이한열(Han-Yeol Lee),장영찬(Young-Chan Jang) 한국전기전자학회 2021 전기전자학회논문지 Vol.25 No.2

본 논문에서는 영상 처리용 12-비트의 10-MS/s 파이프라인 아날로그-디지털 변환기(ADC: analog-to-digital converter)가 제안된다. 제안된 ADC는 샘플-홀드 증폭기, 3개의 stage, 3-비트 플래시 ADC, 그리고 digital error corrector로 구성된다. 각 stage는 4-비트 flash ADC와 multiplying digital-to-analog ADC로 구성된다. 고해상도의 ADC를 위해 제안된 샘플-홀드 증폭기는 gain boosting을 이용하여 전압 이득을 증가시킨다. 제안된 파이프라인 ADC는 1.8V 공급전압을 사용하는 180㎚ CMOS 공정에서 설계되었고 차동 1V 전압을 가지는 1㎒ 사인파 아날로그 입력신호에 대해 10.52-비트의 유효 비트를 가진다. 또한, 약 5㎒의 나이퀴스트 사인파 입력에 대해 측정된 유효비트는 10.12 비트이다. A 12-bit 10-MS/s pipeline analog-to-digital converter (ADC) is proposed for image processing applications. The proposed pipeline ADC consists of a sample and hold amplifier, three stages, a 3-bit flash analog-to-digital converter, and a digital error corrector. Each stage is operated by using a 4-bit flash ADC (FADC) and a multiplying digital-to-analog converter (MDAC). The proposed sample and hold amplifier increases the voltage gain using gain boosting for the ADC with high resolution. The proposed pipelined ADC is designed using a 180-㎚ CMOS process with a supply voltage of 1.8 and it has an effective number of bit (ENOB) of 10.52 bits at sampling rate of 10MS/s for a 1-Vpp differential sinusoidal analog input with frequency of 1 ㎒. The measured ENOB is 10.12 bits when the frequency of the sinusoidal analog input signal is a Nyquist frequency of approximately 5 ㎒.

白松 種子 處理方法에 依한 發芽 生育 調査 硏究

張錫模,李漢烈 順天大學校 農業科學硏究所 1996 農業科學硏究 Vol.10 No.-

This paper presents a germination and growth investigation of Pinus bungeana Zucc. from May 1994 to Dec. 1995. The post-crop site of rhododendron sapling is chosen as a test bed located at forest practice in Sunchon University Major experimental results of seed sowing, sapling progress and root group development can be summarized, as follows. 1. In sowing after refrigeration, the longer refrigeration time leads to the smaller in germination rate and, 6-day seed soaking can raise the germination rate. 2. In sowing after normal storage, the longer storage time also leads to the smaller germination rate. The seed storage of soaking and shading can results in high germination rate. 3. A germination promotion before sowing is needed. To prevent from a damping-off which frequently occurs in Pinaceae, Dachigaren which contains mercury can make good effects. 4. For a good seed production, 2-0 seedling rather than 1-1 seedling results in stronger development of root and branch group.