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자동차 전장용 내고장성 프로세서 기반 차량용 네트워크 CAN 2.0 A, B, FD 통합 IP 설계 및 검증
양정민(Jeongmin Yang),권영수(Youngsu Kwon),신경선(Kyoung-Sun Shin),한지호(Jin-Ho Han),변경진(Kyung-Jin Byun),엄낙웅(Nak-Woong Eum) 대한전자공학회 2015 대한전자공학회 학술대회 Vol.2015 No.6
CAN (controller area network) is a widely used network protocol standard for the automotive applications connecting ECUs and electric devices with low complexity and low cost. In this paper, we describe the implementation and verification procedure of the first CAN 2.0 A, B, FD integrated IP, CAN-ETRI 2.0, based on Fault-Tolerant Vehicle Processor, ALDEBARAN.
ASIP를 이용한 다중 비디오 복호화기 설계 및 최적화
안용조(Yong-Jo Ahn),강대범(Dae-Beom Kang),조현호(Hyun-Ho Jo),지봉일(Bong-Il Ji),심동규(Dong-Gyu Sim),엄낙웅(Nak-Woong Eum) 大韓電子工學會 2011 電子工學會論文誌-CI (Computer and Information) Vol.48 No.1
본 논문은 다양한 비디오 표준의 복호화가 가능한 프로세서를 설계하고, MPEG-2, MPEG-4 및 AVS(Audio video standard)를 이용하여 프로세서의 성능을 검증하였다. 일반적으로 하드웨어 비디오 복호화기는 고속의 복호가 가능하나 설계 및 수정이 어렵다. 반면, 소프트웨어기반의 경우에는 구현이 상대적으로 수월하고 수정이 용이하나, 동작 성능이 낮아 기대하는 속도를 얻기 어렵다. 본 연구에서는 두 가지 연구 설계방법의 장점을 동시에 충족시키는 방법으로 ASIP(Application specific instruction-set processor) 프로세서를 설계하였다. 또한, 비디오 복호화기의 공통 모듈을 연구하여 8개의 모듈로 나누었고, 각 모듈에 공통적으로 적용할 수 있는 다수의 멀티미디어 전용 명령어를 프로세서에 추가하였다. 비디오 복호화기를 위해 개발된 프로세서는 Synopsys 플랫폼 시뮬레이터와 FPGA 보드에서 성능을 평가하였다. 결과적으로 MPEG-2, MPEG-4 및 AVS에 적용하여 평균 37%의 복호 속도를 향상시켰다. In this paper, we present a multi-media processor which can decode multiple-format video standards. The designed processor is evaluated with optimized MPEG-2, MPEG-4, and AVS (Audio video standard). There are two approaches for developing of real-time video decoders. First, hardware-based system is much superior to a processor-based one in execution time. However, it takes long time to implement and modify hardware systems. On the contrary, the software-based video codecs can be easily implemented and flexible, however, their performance is not so good for real-time applications. In this paper, in order to exploit benefits related to two approaches, we designed a processor called ASIP(Application specific instruction-set processor) for video decoding. In our work, we extracted eight common modules from various video decoders, and added several multimedia instructions to the processor. The developed processor for video decoders is evaluated with the Synopsys platform simulator and a FPGA board. In our experiment, we can achieve about 37% time saving in total decoding time.
A Low Power Design of H.264 Codec Based on Hardware and Software Co-design
Seongmo Park(박성모),Sukho Lee(이석호),KyoungSeon Shin(신경선),Jae-Jin Lee(이재진),Moo-Kyoung Chung(정무경),Jun-Young Lee(이준영),Nak-Woong Eum(엄낙웅) 한국통신학회 2008 정보와 통신 Vol.25 No.12
In this paper, we present a low-power design of H.264 codec based on dedicated hardware and software solution on EMP(ETRI Multi-Core Platform). The dedicated hardware scheme has reducing computation using motion estimation skip and reducing memory access for motion estimation. The design reduces data transfer load to 66% compared to conventional method. The gate count of H.264 encoder and the performance is about 455k and 43Mhz@30fps with D1(720×480) for H.264 encoder. The software solution is with ASIP(Application Specific Instruction Processor) that it is SIMD(Single Instruction Multiple Data), Dual Issue VLIW(Very Long Instruction Word) core, specified register file for SIMD, internal memory and data memory access for memory controller, 6 step pipeline, and 32 bits bus width. Performance and gate count is 400㎒@30fps with CIF(Common Intermediated Format) and about 100k per core for H.264 decoder.
ASIC Front-Ent 설계용 CAD 시스템 LODECAP:Logic Design CAPture
김정범,이성봉,김상필,배영환,박인학,박영수,백영석,조한진,엄낙웅 대한전자공학회 1995 CAD 및 VLSI 설계연구회지 Vol.4 No.1
An ASIC design system. called LODECAP (LOgic DEsign CAPture), has been developed by ETRI CAD engineers. LODECAP supports two design methods : the traditional logic design style and advanced design style using logic synthesis system. Input data can be schematic, logic equation, truth table and state transition table captured by the dedicated graphic editors. Output data is netlist in EDIF or XNF format. All kinds of user-defined design data are automatically converted to VHDL programs and verified by VHDL simulator. LODECAP has already distributed to 37 universities until September 15 1995. Now, it is used in real design field by companies who want to develop ASIC chips in ETRI process facility.