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DNA Amplified Fingerprinting 기법을 이용한 Salmonella pullorum과 Salmonella gallinarum의 다형성 비교 분석
김연수,김상균,송원철,황의경,Kim, Yeon-Soo,Kim, Sang-Kyun,Song, Won-Chul,Hwang, Eui-Kyung 대한수의학회 2001 大韓獸醫學會誌 Vol.41 No.3
This study was performed to detect the Salmonella genus-specific DNA marker for comparing of polymophisms between S pullorum and S gallinarum by using PCR amplified techniques. A total of ten primers were used to detect DNA polymorphisms from S pullorum and S gallinarum. The number of DAF bands detected per each primer varied from 26 to 45, with an average of 32.7 using 10 primers. A total of 327 DAF bands were generated and among them 123 bands were polymorphic(37.6%). These DNA amplified fingerprinting(DAF) specific bands for S pullorum and S gallinarum were observed from all primers. For S pullorum, GEN 60-04, GEN 70-04 and GEN 70-03 primers showed a high level of polymorphism with 0.79, 0.70 and 0.57, respectively. But GEN 60-05 primer did not show a level of polymorphism. For S gallinarum, GEN 70-03, 60-04, 60-07, 70-05 and 70-04 primers showed a higher a low level of polymorphism from 0.16 to 0.28. Each five strains of S pullorum and S gallinarum were isolated from chickens showed typical clinical signs related with infection of pullorum disease or fowl typhoid at commercial chicken farms. DNA markers of these strains produced by GEN 70-04, GEN 70-05 and GEN 70-08 showed significant difference of band patterns between S pullorum and S gallinarum. These DNA markers could be used for comparison of DNA marker polymorphism between S pullorum and S gallinarum as well as rapid diagnosis of fowl typhoid and pullorum disease of domestic fowls.
CMOS 트랜지스터의 채널 폭 및 길이 변화에 따른 RF 특성분석 및 최적화
최정기,이상국,송원철,Choi, Jeong-Ki,Lee, Sang-Gug,Song, Won-Chul 대한전자공학회 2000 電子工學會論文誌-SD (Semiconductor and devices) Vol.37 No.8
0.35m CMOS공정을 이용하여 MOSFET의 RF특성을 평가하였다. 채널길이(L-0.25~0.8m)와 채널폭(W=50~600m) 및 바이어스 전압의 변화에 따른 RF특성을 분석하였으며, 차단주파수$f_T$는 최대 22GHz, 최대공진주파수($f_{max}$)는 최대 28GHz의 값을 얻었다. 채널폭의 변화에 대해서 차단주파수는 영향을 받지 않았으며, 최대공진주파수는 감소하는 경향을 보였고, 채널길이 증가에 대해서는 차단주파수 및 최대공진주파수 모두 감소하는 경향을 나타내었다. 최소잡음지수는 채널폭이 증가할수록 감소하고 채널길이가 증가할수록 증가하는 경향을 얻었는데, 2GHz에서 최소 0.45dB의 값을 얻었다. 평가결과로부터 0.35m CMOS공정이 2GHz대역의 상업용 RFIC 구현에 충분한 RF특성을 보유하고 있음을 확인할 수 있었으며, 바이어스 및 채널폭과 길이변화에 대한 CMOS 트랜지스터의 RF 특성분석을 통하여 RF 회로설계에 대한 지침을 제시하였다. MOS transistors are fabricated and evaluated for RF IC applications such as mobile communication systems using 0.35m CMOS process. Characteristics of MOSFETs are analyzed at various channel length, width and bias conditions. From the analysis, cut-off frequency ($f_T$) is independent on channel width but maximum oscillation frequency ($f_{max}$) tends to derease as the channel width increases. As channel length increases, $f_T$ and fmax decrease. $f_T$ is 22GHz and fmax is 28GHz at its maximum value. High frequency noise performance is improved with larger channel width and smaller channel length at same bias conditions. NFmin at 2GHz is 0.45dB as a minimum value. From the evaluation, MOSFETs designed using 0.35m CMOS process demonstrated a full potential for the commercial RF ICs for mobile communication systems near 2GHz. And optimization methods of the CMOS transistors for RF applications are presented in this paper.
작은 정현파입력의 50% Duty Ratio 디지털 클럭레벨 변환기 설계
박문양,이종열,김욱,송원철,김경수,Park, Mun-Yang,Lee, Jong-Ryul,Kim, Ook,Song, Won-Chul,Kim, Kyung-Soo 한국통신학회 1998 韓國通信學會論文誌 Vol.23 No.8
휴대용 기기에서 자체 발진하여 클럭원으로 사용되는 TCXO의 출력과 같은 작은 진폭(400mV)의 정현파 입력을 내부 논리회로의 클럭원으로 사용하기 위한 파형정형 및 50%의 듀티 비(duty ratio)의 출력을 가지는 새로운 디지털 클럭레벨 변환기를 설계, 개발 하였다. 정, 부 두 개의 비교기, RS 래치, 차아지 펌프, 기준 전압 발생기로 구성된 새로운 신호 변환회로는 출력파형의 펄스 폭을 감지하고, 이 결과를 궤환루프로 구성하여 입력 비교기 기준 전압단자로 궤환시킴으로서 다지털 신호레벨의 정확한 50%의 듀티 비를 가진 출력을 생성할 수 있다. 개발한 레벨변환기는 ADC등의 샘플링 클럭원, PLL 또는 신호 합성기의 클럭원으로 사용할 수가 있다. 설계는 $0.8\mu\textrm{m}$ double metal double poly analog CMOS 공정을 사용하고, BSIM3 model을 사용하였으며, 실험결과 370mV의 정현파 입력율 50 + 3%의 듀티 비를 가진 안정된 논리레벨 출력 동작특성을 얻을 수 있었다. A new digital clock level translator has been designed in order to produce a clock source of the internal logic circuits. The translator output has 50% duty ratio from small sinusoidal input such as TCXO which oscillates itself in poratable components. The circuit consists of positive and negative comparators, RS latch, charge pump, and reference vol- tage generator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator reference, producing output waveform with valid 50% duty ratio of the digital signal level. The designed level translator can be used as a sampling clock source of ADC, PLL and the colck source of the clock synthesizer. The circuit wasdesigned in a 0.8.mu.m analog CMOS technology with double metal, double poly, and BSIM3 circuit simulation model. From our experimental results, a stable operating characteristics of 50 +3% duty ratio was obtained from the sinusoidal input wave of 370 mV.
복제 V-I 변환기를 이용한 3.3V 30mW 200MHz CMOS 업 컨버젼 믹서
권종기,김욱,오창준,이종렬,송원철,김경수,Kwon, Jong-Kee,Kim, Ook,Oh, Chang-Jun,Lee, Jong-Ryul,Song, Won-Chul,Kim, Kyung-Soo 한국통신학회 1997 韓國通信學會論文誌 Vol.22 No.9
Code Division Multiple Access(CDMA) 통신방식을 채택한 휴대용 이동전화기의 중간주파수(intermediate frequency: IF) 아날로그 IC의 송신부를 구성하고 있는 저전력 선형특성을 지닌 CMOS 업 컨버젼 믹서(upconversion mixer)의 설계, 제작 및 특성 측정에 대해 기술하였다. 업 컨버젼 믹서의 구조는 복제 V-I 변환기를 사용하여 그 선형성을 확장한 형태의 회로기술을 채택하였다. 설계된 업 컨버젼 믹서는 $0.8{\mu}\textrm{m}$ N-well CMOS 2-poly/2-metal 공정기술을 사용하여 IC로 구현하였으며 그 크기는 $0.53mm{\times}0.92mm$이다. 소비전력은 3.3V 공급전원과 130MHz Local Oscillation(LO) 클럭이 인가되었을 때 30mW이다. 출력의 1dB compression 특성은 2-tone 입력신호가 인가되고 $25{\Omega}$ 부하를 가질 때에 -28dBm이다. In this paper, the power efficient linear upconversion mixer which is a functional circuit in transmit path of intermediate frequency(IF) part of Code Division Multiple (CDMA) cellular phone was explained. In generally, the low CMOS devices limits the implementation of upconversion mixer especially for lower loads. Using replica transconductor, the linear range is extended up to the limit. Thiscircuit was imprlemented using $0.8{\mu}\textrm{m}$ N-well CMOS technology with 2-poly/2-metal. The active area of chip is $0.53mm{\times}0.92mm$. The power consumption is 30mW with 3.3V suply voltage. The 1dB conpression characteristics is -27.3dB with $25{\Omega}$. load and being applied by 2-tone input signal. The mixer operates properly above 200MHz.
DNR 반응조에서 슬러지 탈질조에 반류수 주입이 영양염류 제거에 미치는 영향
이병헌 ( Byung Hun Lee ),송원철 ( Won Chul Song ),황은주 ( Eun Jo Hwang ),이민규 ( Min Gyu Lee ),김중균 ( Joong Kyun Kim ) 한국수처리학회 2003 한국수처리학회지 Vol.11 No.2
N/A DNR process was developed for the N, P removal of the low organic materials concentration wastewater like domestic circumstances. This study was conducted to improve the removal rate of N, P and endogenous denitrification rate by inflowing the recycle water of wastewater treatment plant to sludge denitrifier. It defends the inhibition of phosphorus release from anaerobic reactor. To investigate effects of nitrogen removal in inflowing the recycle water of Modified DNR, the process is accomplished by three steps. First, compared the removal rate between DNR and Modified DNR in utilizing methanol as external carbon. Second, grasped whether use the recycle water as external carbon or not. And third, studied the removal effects of N, P in inflowing the recycle water to sludge denitrifier. At that result, Modified DNR were higher about 78%, 74% in the removal rate of N,P than DNR 70%. 60%. As inflowing the recycle water to sludge denitrifier, the nitrogen removal rate was 70.4% in spite of the low C/N ratio. It was similar to DNR removal rate. It was estimated that Modified DNR process show the better treatment effects than DNR in the low concentration wastewater treatment, it should be recognized that this process is suitable for DNR improvement.