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저면적 12비트 1MSps 연속 근사형 레지스터 아날로그-디지털 변환기 설계
성명우(Myeong-U Seong),이정훈(Jung-Hoon Lee),류지열(Jee-Youl Ryu) 한국정보기술학회 2015 한국정보기술학회논문지 Vol.13 No.2
This paper proposes a low area 12-bit 1MSps SAR ADC(Successive Approximation Register Analog-to-Digital Converter). The proposed circuit is designed using Magnachip/SK Hynix 1-Poly 6-Metal 0.18-μm CMOS process, and it is powered by a 1.8-V supply. Total chip area is reduced by replacing the MIM capacitors with MOS capacitors instead of the capacitors consisting of overall part in chip area. We designed optimized circuit as compared to conventional circuits by reducing the unit capacitors and number of the total capacitors to reduce power dissipation. The proposed circuit in this paper showed improved power dissipation of 1.93mW, and chip area of 0.51mm² as compared to conventional research results at the input frequency of 100kHz and power supply of 1.8V. The designed circuit also showed high SNDR(Signal-to-Noise Distortion Ratio) of 70.51dB, and excellent effective number of bits of 11.4bits.
성명우(Myeong-U Seong),류지열(Jee-Youl Ryu) 한국정보기술학회 2018 한국정보기술학회논문지 Vol.16 No.1
This paper presents high-precision low-cost digital portable hardness tester using the Leeb rebound hardness test method. The Leeb rebound test method is generally easier to measure, and more accurate than other types of hardness testing methods. This method is used on all metals, except in condition where the test metal structure or surface conditions would introduce too much variations. This portable method is also used for testing efficiently hardness of surface and unreachable edges of large metal workpiece(mainly above 1kg). The proposed hardness tester consists of sensor probes(impact devices) of 7-type to measure Leeb rebound and embedded system unit for its control and signal processing. This hardness tester showed resolution of more than 20%, measurement accuracy of more than 25%, cost effective of 33% and response time of 15msec for the various test samples as compared to conventional hardness tester. We believe that this tester is widely used in the metal industries to measure hardness.
시스템-온-칩을 위한 12비트 1MSps 연속 근사형 아날로그-디지털 변환기 설계
최성규,성명우,김성우,류지열 한국정보기술학회 2014 한국정보기술학회논문지 Vol. No.
This paper proposes a 12-bit 1MSps SAR ADC(Successive Approximation Register Analog-to-Digital Converter) for SoC(System-on-Chip). The proposed circuit is designed using Magnachip/SK Hynix 0.18㎛ CMOS 1Poly-6Metal process, and it is powered by 1.8 supply. To reduce chip area and power dissipation, we minimized unit capacitor area and number of the total capacitors, and designed the circuit considering optimization as compared to conventional circuits. The proposed circuit in this paper showed high SNDR(Signal-to-Noise Distortion Ratio) of 70.03dB, and excellent effective bit number of 11.34-bit as compared to conventional research results. The designed circuit also showed low power dissipation of 5.5mW, and small chip area of 0.56mm2. The proposed ADC is applicable for the signal conversion of the industry system application. 본 논문에서는 시스템-온-칩을 위한 12비트 1MSps 연속 근사형 레지스터 아날로그-디지털 변환기를 제안한다. 제안하는 회로는 Magnachip/SK Hynix 0.18㎛ CMOS 1Poly-6Metal 공정 기술을 이용하여 설계하였고, 1.8V 공급전압에서 동작한다. 칩 면적과 소비전력을 줄이기 위하여 기존의 회로에 비해 단위 커패시터 및 전체 커패시터 수를 줄이고, 최적화를 고려하여 설계하였다. 본 논문에서 제안하는 회로는 1.8V 공급전압과 입력신호의 주파수가 100KHz일 때, 기존 연구 결과에 비해 70.03dB의 높은 SNDR(Signal-to-Noise Distortion Ratio)과 11.34비트의 우수한 유효비트 특성을 보였다. 또한 설계된 회로는 5.5mW의 낮은 소비전력 특성과 0.56mm2의 작은 칩 면적 특성을 보였다. 제안하는 아날로그-디지털 변환기는 산업용 시스템의 신호 변환 응용에 적용된다.
Design of a CMOS Current-reuse LC VCO
Habib Rastegar,성명우,류지열 한국과학기술원 반도체설계교육센터 2018 IDEC Journal of Integrated Circuits and Systems Vol.4 No.1
This paper presents a cascode CMOS current-reuse voltage-controlled oscillator (LC VCO) for 24GHz automotive collision radar. This circuit is designed using 65nm CMOS technology. The VCO in modified current-reuse configuration where transistors are biased in subthreshold region to save power consumption. This scheme is utilized to simultaneously reduce the power consumption, and increase the transconductance and gain of the VCO circuit. The capacitive-feedback technique, including two series capacitors is also used to improve voltage swing of output ports under low power and low supply voltage conditions. This circuit also has fully-differential configuration to reduce RF noise and harmonic distortion. The proposed VCO showed phase noise of -123dBc/Hz at 1MHz offset, and power consumption of 321μW at power supply of 950mV with a FOM of -204 dBc/Hz. The die area occupied 0.35mm2.
시스템-온-칩을 위한 12비트 1MSps 연속 근사형 아날로그-디지털 변환기 설계
최성규(Seong-Kyu Choi),성명우(Myeong-U Seong),김성우(Sung-Woo Kim),류지열(Jee-Youl Ryu) 한국정보기술학회 2014 한국정보기술학회논문지 Vol.12 No.5
This paper proposes a 12-bit 1MSps SAR ADC(Successive Approximation Register Analog-to-Digital Converter) for SoC(System-on-Chip). The proposed circuit is designed using Magnachip/SK Hynix 0.18㎛ CMOS 1Poly-6Metal process, and it is powered by 1.8 supply. To reduce chip area and power dissipation, we minimized unit capacitor area and number of the total capacitors, and designed the circuit considering optimization as compared to conventional circuits. The proposed circuit in this paper showed high SNDR(Signal-to-Noise Distortion Ratio) of 70.03dB, and excellent effective bit number of 11.34-bit as compared to conventional research results. The designed circuit also showed low power dissipation of 5.5mW, and small chip area of 0.56mm2. The proposed ADC is applicable for the signal conversion of the industry system application.
Design of Programmable Finite Impulse Response Filter
Jae-Il Chun(천재일),Ye-Ji Choi(최예지),Keun-Pil Kil(길근필),Myeong-U Sung(성명우),Shin-Gon Kim(김신곤),Murod Kurbanov(무로드 쿠르바노프),Delwar Tahesin Samira(델워 타헤신 사미라),Abrar Siddique(시디크 아브라르),Prangyadarsini Behera(파랑야다시 한국정보통신학회 2019 한국정보통신학회 종합학술대회 논문집 Vol.23 No.2