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Design of a CMOS Current-reuse LC VCO
Habib Rastegar,성명우,류지열 한국과학기술원 반도체설계교육센터 2018 IDEC Journal of Integrated Circuits and Systems Vol.4 No.1
This paper presents a cascode CMOS current-reuse voltage-controlled oscillator (LC VCO) for 24GHz automotive collision radar. This circuit is designed using 65nm CMOS technology. The VCO in modified current-reuse configuration where transistors are biased in subthreshold region to save power consumption. This scheme is utilized to simultaneously reduce the power consumption, and increase the transconductance and gain of the VCO circuit. The capacitive-feedback technique, including two series capacitors is also used to improve voltage swing of output ports under low power and low supply voltage conditions. This circuit also has fully-differential configuration to reduce RF noise and harmonic distortion. The proposed VCO showed phase noise of -123dBc/Hz at 1MHz offset, and power consumption of 321μW at power supply of 950mV with a FOM of -204 dBc/Hz. The die area occupied 0.35mm2.
An Integrated High Linearity CMOS Receiver Frontend for 24-GHz Applications
Habib Rastegar,Jee-Youl Ryu 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.5
Utilizing a standard 130-nm CMOS process, a RF frontend is designed at 24 GHz for automotive collision avoidance radar application. Single IF direct conversion receiver (DCR) architecture is adopted to achieve high integration level and to alleviate the DCR problem. The proposed frontend is composed of a two-stage LNA and downconversion mixers. To save power consumption, and to enhance gain and linearity, stacked NMOS-PMOS gm-boosting technique is employed in the design of LNA as the first stage. The switch transistors in the mixing stage are biased in subthreshold region to achieve low power consumption. The single balanced mixer is designed in PMOS transistors and is also realized based on the well-known folded architecture to increase voltage headroom. This frontend circuit features enhancement in gain, linearity, and power dissipation. The proposed circuit showed a maximum conversion gain of 19.6 dB and noise figure of 3 dB at the operation frequency. It also showed input and output return losses of less than -10 dB within bandwidth. Furthermore, the port-to-port isolation illustrated excellent characteristic between two ports. This frontend showed the third-order input intercept point (IIP3) of 3 dBm for the whole circuit with power dissipation of 6.5 mW from a 1.5 V supply.
A 2 GHz 20 dBm IIP3 Low-Power CMOS LNA with Modified DS Linearization Technique
Habib Rastegar,Jae-Hwan Lim,류지열 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.4
The linearization technique for low noise amplifier (LNA) has been implemented in standard 0.18-µm BiCMOS process. The MOS-BJT derivative superposition (MBDS) technique exploits a parallel LC tank in the emitter of bipolar transistor to reduce the second-order non-linear coefficient (gm2) which limits the enhancement of linearity performance. Two feedback capacitances are used in parallel with the base-collector and gate-drain capacitances to adjust the phase of third-order non-linear coefficients of bipolar and MOS transistors to improve the linearity characteristics. The MBDS technique is also employed cascode configuration to further reduce the second-order nonlinear coefficient. The proposed LNA exhibits gain of 9.3 dB and noise figure (NF) of 2.3 dB at 2 GHz. The excellent IIP3 of 20 dBm and low-power power consumption of 5.14 mW at the power supply of 1 V are achieved. The input return loss (S11) and output return loss (S22) are kept below -10 dB and -15 dB, respectively. The reverse isolation (S12) is better than -50 dB.
An Integrated High Linearity CMOS Receiver Frontend for 24-GHz Applications
Rastegar, Habib,Ryu, Jee-Youl The Institute of Electronics and Information Engin 2016 Journal of semiconductor technology and science Vol.16 No.5
Utilizing a standard 130-nm CMOS process, a RF frontend is designed at 24 GHz for automotive collision avoidance radar application. Single IF direct conversion receiver (DCR) architecture is adopted to achieve high integration level and to alleviate the DCR problem. The proposed frontend is composed of a two-stage LNA and downconversion mixers. To save power consumption, and to enhance gain and linearity, stacked NMOS-PMOS $g_m$-boosting technique is employed in the design of LNA as the first stage. The switch transistors in the mixing stage are biased in subthreshold region to achieve low power consumption. The single balanced mixer is designed in PMOS transistors and is also realized based on the well-known folded architecture to increase voltage headroom. This frontend circuit features enhancement in gain, linearity, and power dissipation. The proposed circuit showed a maximum conversion gain of 19.6 dB and noise figure of 3 dB at the operation frequency. It also showed input and output return losses of less than -10 dB within bandwidth. Furthermore, the port-to-port isolation illustrated excellent characteristic between two ports. This frontend showed the third-order input intercept point (IIP3) of 3 dBm for the whole circuit with power dissipation of 6.5 mW from a 1.5 V supply.
A 2 ㎓ 20 ㏈m IIP3 Low-Power CMOS LNA with Modified DS Linearization Technique
Habib Rastegar,Jae-Hwan Lim,Jee-Youl Ryu 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.4
The linearization technique for low noise amplifier (LNA) has been implemented in standard 0.18-㎛ BiCMOS process. The MOS-BJT derivative superposition (MBDS) technique exploits a parallel LC tank in the emitter of bipolar transistor to reduce the second-order non-linear coefficient (gm2) which limits the enhancement of linearity performance. Two feedback capacitances are used in parallel with the base-collector and gate-drain capacitances to adjust the phase of third-order non-linear coefficients of bipolar and MOS transistors to improve the linearity characteristics. The MBDS technique is also employed cascode configuration to further reduce the second-order nonlinear coefficient. The proposed LNA exhibits gain of 9.3 ㏈ and noise figure (NF) of 2.3 ㏈ at 2 ㎓. The excellent IIP3 of 20 ㏈m and low-power power consumption of 5.14 ㎽ at the power supply of 1 V are achieved. The input return loss (S11) and output return loss (S22) are kept below -10 ㏈ and -15 ㏈, respectively. The reverse isolation (S12) is better than -50 ㏈.
A 2 GHz 20 dBm IIP3 Low-Power CMOS LNA with Modified DS Linearization Technique
Rastegar, Habib,Lim, Jae-Hwan,Ryu, Jee-Youl The Institute of Electronics and Information Engin 2016 Journal of semiconductor technology and science Vol.16 No.4
The linearization technique for low noise amplifier (LNA) has been implemented in standard $0.18-{\mu}m$ BiCMOS process. The MOS-BJT derivative superposition (MBDS) technique exploits a parallel LC tank in the emitter of bipolar transistor to reduce the second-order non-linear coefficient ($g_{m2}$) which limits the enhancement of linearity performance. Two feedback capacitances are used in parallel with the base-collector and gate-drain capacitances to adjust the phase of third-order non-linear coefficients of bipolar and MOS transistors to improve the linearity characteristics. The MBDS technique is also employed cascode configuration to further reduce the second-order nonlinear coefficient. The proposed LNA exhibits gain of 9.3 dB and noise figure (NF) of 2.3 dB at 2 GHz. The excellent IIP3 of 20 dBm and low-power power consumption of 5.14 mW at the power supply of 1 V are achieved. The input return loss ($S_{11}$) and output return loss ($S_{22}$) are kept below - 10 dB and -15 dB, respectively. The reverse isolation ($S_{12}$) is better than -50 dB.
High-Gain and Low-Power Power Amplifier for 24-GHz Automotive Radars
Shin-Gon Kim,Habib Rastegar,Min Yoon,Chul-Woo Park,Kyoungyong Park,Sookyoung Joung,Jee-Youl Ryu 보안공학연구지원센터 2015 International Journal of Smart Home Vol.9 No.2
This paper presents a high gain and low power 24-GHz power amplifier (PA) for the short range automotive radar. The proposed circuit is implemented using TSMC 0.13-μm RF CMOS (fT/fmax=120/140 GHz) technology, and it is powered by a 1.5-V supply. To improve power gain of the amplifier, it has a 2-stage cascode scheme. This circuit uses transmission lines to reduce total chip size instead of real bulky inductors for input and output impedance matching. The layout techniques for RF (radio frequency) are used to reduce parasitic capacitances at the band of 24 GHz. The proposed RF amplifier has low cost and low power dissipation since it is realized using all CMOS processes. The proposed circuit showed the smallest chip size of 0.12 mm2, the lowest power dissipation of 44.3 mW and the highest power gain of 24.04 dB as compared to recently reported research results.
FPGA Implementation of Programmable Digital FIR/IIR Filter
Pushpalatha Chandrasekar,Myeong-U Sung,Geun-Ho Choi,Habib Rastegar,Shin-Gon Kim,Murod Kurbanov,Seung-Kyu Choi,Keun-Pil Kil,Jee-Youl Ryu,Seok-Ho Noh,Min Yoon 한국정보통신학회 2016 2016 INTERNATIONAL CONFERENCE Vol.8 No.1
This paper presents FPGA implementation for programmable digital FIR/IIR filter. Sine wave generation and detecting frequency of the sine wave signals have been proposed. Simulation results show that the system has the ability to provide a better frequency response for various cut-off frequencies. The design has been implemented in Altera, cyclone II family EP2C70F89618 device using Quartus software.