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HiPi 버스를 갖는 캐쉬 기반형 멀티프로세서 시스템의 성능 평가
고석범,박경,황인석,강인곤,김영천 전북대학교 공업기술연구소 1991 工學硏究 Vol.22 No.-
Shared bus structure is usually used for a small-scaled multiprocessor system because of easy implementation and low cost But, overall performance of system is limited by bandwidth and transfer rate of the bus. Shortcomes of this structured multiprocessor system sre the shared bus bolttleneck and the increasement of the memory access time. these problems can be solved by using the multiple cache memory and the improvement of bus protocol. In this paper, multiprocessor system using HiPi bus and multiple cache memory is considered and described to improve the performance of time shared bus structure. HiPi bus uses pended protocol to increase the bus capacity. Cache to cache transfer mode is proposed to enhance the performance of HiPi bus. The performance of multiprocessor system with HiPi bus and that of multiprocessor system with modified HiPI bus are analyzed and compared. An analytical model for this system is described by Markov state diagram to compute the probability of each state. And, the modeling and simulation are done using SLAM III simulation language. The number of processors, hit ratio and the probability of the read operation are used as the input parameters. The utilization of processors,. address/data bus, and memory are measured and evaluated.