��키 배리어 쏘라 쎌

崔元銀,張宜久 중앙대학교 기술과학연구소 1981 기술과학연구소 논문집 Vol.8 No.-

The properties of Schottky barrier solar cell on n-type silicon have been investigated. Naturally formed insulation layer have been used for the insulating fillm on silicon wafer. The interfacial layer plays an important role in reducing the open circuit voltage and the efficiency of the solar cell. Measurement have been made of the electrical and optical properties of Au-nSi solar cells. It is shown that the efficiency of the cell increase at first with the interfacial layer thickness δ, and after acquiring a maximum value falls with a further increase of δ

유도결합 플라즈마를 이용한 PZT 박막 식각특성에 관한 연구

안태현,김창일,서용진,장의구 중앙대학교 기술과학연구소 1999 기술과학연구소 논문집 Vol.29 No.-

졸-겔 법을 통해 PZT 박막을 2500 Å을 정착하였고 열처리를 통해 페로브스카이트 상을 얻었다. ICP 장비를 이용하여 Ar(20)/??/?? 가스 조합에 따른 플라즈마에서 기판 온도를 변화시키면서 PZT식각을 수행하였다. 가스 조건으로는 Ar/??:20/80, 기판온도는 80℃, 소오스 파워 500 W, dc 바이어스 전압은 -300 V, 반응로 압력 200 mTorr에서 PZT대 TR과 Pt의 식각 선택비는 각각 0.9, 3.9를 각각 얻었고, PZT 식각속도는 2450 A/min을 얻었다. ?? 가스는 상온에서 응결하므로 공정 반응로까지 이어지는 가스관에 정온 코일을 감아주기 때문에 가판온도을 올리기 전에 이미 데워져 있기 때문으로 여겨진다. 그러나 식각속도는 증가하였다. 이는 B와 BCl의 라디칼이 O와 결합하여?? 그리고/또는 ??의 휘발생 물질을 생성하여 metallic Pb, Zr, Ti가 표면으로 많이 노출되어 Cl 라디칼과 결합이 용이하기 때문에 식각속도가 증가한다고 판단된다. 또한 /?? 가스조건과 80°이상의 식각 프로파일을 얻었다. In this study, PZT etching was performed using plannar inductively coupled Ar(20)/??/?? plasma. The etch rate of PZT film was 2450 Å/min at Ar/?? gas mixing ratio and substrate temperature of 80℃. As increasing content of ??, the selectivities of PZT to Pr and PR increase linearly, and are directly proportional to substrate temperature in less than amount of 50% ??. However, at the condition over 50% ??, the etch rate of PZT have no dependence on the substrate temperature. The selectivities of PZT to Pt and PR were 3.9 and 0.9, respectively at the Ar(20)/??(80) gas mixing ratio and the substrate temperature of 80℃. X-ray photoelectron spectroscopy (XPS) analysis for film composition of etched PZT surface was utilized. The chemical bond of PbO is broken by ion bombardment and Cl radical, and the peak of metal Pb in a Pb 4f narrow can begins to appear upon etching. As increasing additive ?? content, the relative content of oxygen decreases rapidly, in contrast with etch rate of PZT thin film. So, we thought content of oxygen decreases rapidly, in contrast with etch rate of PZT thin film. So, we thought content of oxygen decreases rapidly, in contrast with etch rate of PZT thin film increased because abundant B and BCl radicals made volatile oxy-compound such as ?? and/or ?? bond. To understand etching mechanism, Langmuir probe and optical emission spectroscopy (OES) analysis were utilized for plasma diagnostic.

Schottky Barrier Diode

張宜久,崔元銀 중앙대학교 기술과학연구소 1975 기술과학연구소 논문집 Vol.2 No.-

This paper describes the characteristics of a Schottky barrier diode of Al-coated n-type silicon (Al-nSi). The surface of the silicon wafer is cleaned by a physical method(sputter cleaning) after pre-cleaned by the standard chemical cleaning method. SiO_2 layer is formed around the Al layer on the Si wafer for the edge passivation. The barrier height is determined to be 0.69eV by both of the saturation current of Ⅰ-Ⅴ charateristics and the temperature dependence of forward cenrrent. It is to note that the characteristics of the diode is fairly improved by the effort of minimizing the formation of the interfacial layer. The specific contact resistance at zero bias, Rc, is an important figure for the transport characteristic of a metal-semiconductor barrier under operating conditions. The values of Rc have been calculated for metal-Si barrier on n-type. The experimental results of Rc depend on the density of forward current and field emission.

질화된 MOS커패시터의 C-T특성 ( C-T Characteristics of Nitridized MOS Capacitor )

장의구,최원은,서용진,최현식,유석빈 대한전자공학회 1988 대한전자공학회 학술대회 Vol.1988 No.7

솔더범프와 TiW/Cu/electroplating Cu UBM 층과의 금속간 화합물 형성과 범프 전단력에 관한 연구

장의구,김남훈,김남규,엄준철 한국전기전자재료학회 2004 전기전자재료학회논문지 Vol.17 No.3

The joint strength and fracture surface of Sn-Pb solder bump in photo diode packages after isothermal aging testing were studied experimentally. Cu/Sn-Pb solders were adopted, and aged for up to 900 hours at 12$0^{\circ}C$ and 17$0^{\circ}C$ to analyze the effect of intermetallic compound(IMC). In 900-hour aging experiments, the maximum shea strength of Sn-Pb solder decreased by 20% and 9%. The diffraction patterns of Cu$_{6}$Sn$_{5}$, scallop-shape IMC, and planar-shape Cu$_3$Sn were observed by Transmission Electron Microscopy (TEM).EM).

153 FC-BGA에서 솔더접합부의 신뢰성 향상에 관한 연구

장의구,김남훈,유정희,김경섭 한국마이크로전자및패키징학회 2002 마이크로전자 및 패키징학회지 Vol.9 No.3

PBGA에 비해 상대적으로 큰 칩을 실장하는 고속 SRAM용 153 FC-BGA을 대상으로 2차 솔더접합부의 신뢰성을 평가하였다. 실험은 열사이클 시험에서 발생하는 단면과 양면 실장, 패키지 구조, 언더 필 재료, 기판의 종류와 두께, 솔더 볼의 크기에 따른 영향을 분석하였다. BT기판의 두께가 0.95mm에서 1.20mm로 증가하고, 낮은 영률 의 언더 필 재료에서 솔더접합부의 피로 수명이 30% 향상됨을 확인하였다. 또한 솔더 볼의 크기가 0.76 mm에서 0.89mm로 증가하면, 솔더접합부에서 균열에 대한 저항성은 2배 정도 증가하였다. The 2nd level solder joint reliability of 153 FC-BGA for high-speed SRAM (Static Random Access Memory) with the large chip on laminate substrate comparing to PBGA(Plastic Ball Grid Array) was studied in this paper. This work has been done to understand an influence as the mounting with single side or double sides, structure of package, properties of underfill, properties and thickness of substrate and size of solder ball on the thermal cycling test. It was confirmed that thickness of BT(bismaleimide tiazine) substrate increased from 0.95 mm to 1.20 mm and solder joint fatigue life improved about 30% in the underfill with the low young's modulus. And resistance against the solder ball crack became twice with an increase of the solder ball size from 0.76 mm to 0.89 mm in solder joints.

Chemical Mechanical Polishing 공정기술의 이해

장의구 한국전기전자재료학회 1999 전기전자재료 Vol.12 No.10

매몰채널 pMOSFET의 짧은 채널 특성 개선에 관한 연구

이철인,장의구 중앙대학교 기술과학연구소 1994 기술과학연구소 논문집 Vol.24 No.-

We have studied the characteristics of pMOSFET with short channel effects of buried channel. Threshold voltage dependence and potential distribution with ion implantation condition and impurity profile of channel region were studied. MOSFET has buried channel in the depth of about 0.15㎛ by counter-doped boronion implantation for threshold voltage adjustment. In this paper, we have presented a method to extract process and design by computer simulation.

텅스텐 실리사이드막의 물리적 전기적 특성

김태형,김창일,장의구 중앙대학교 생산공학연구소 1992 생산공학연구소 논문집 Vol.1 No.1

W-polycide(??/n+poly-Si)구조로 poly-Si막과 ?? 막 두께를 변화시켜 LPCVD를 이용하여 증착하고 온도를 달리하여 열처리하였으며 이러한 텅스텐 폴리사이드특성에 poly-Si막과 ??막 두께, 열처리 온도가 미치는 영향을 조사하였다. ??막 두께가 증가함에 따라 면저항은 감소하고 스트레스는 증가하였으며 reflectance는 거의 일정하였다. poly-Si막 두께증가에 따라 스트레스는 다소 증가하였으나 면저항과 reflectance는 일정하였고 열처리 온도 증가에 따라서는 면저항과 reflectance는 감소하였고 스트레스는 증가하였다. 또한 조성(Si/W)비의 변화를 관찰하였다. Poly-Si and ?? films in polycide(??/n+poly-Si) structure were deposited by LPCVD to changed thickness, and then were annealed at various temperatures. The effect of poly-Si and ?? film thickness and annealing temperature on the W-polycide properties was investigated. With increasing ?? film thickness, it has been observed that sheet resistance decreases, stress increases, and reflectance in constant. It has also been observed that as poly-Si film thickness increases, stress increases a little bit, while sheet resistance and reflectance are constant. As the annealing temperature gets higher, the decrease in sheet resistance and reflectance, and the increase in stress have been observed. Also, the variation of composition(Si/W) ratio is examined.

MIS 太陽電池

張宜久 중앙대학교 기술과학연구소 1982 기술과학연구소 논문집 Vol.9 No.-

The insulation layers have been used for the insulating film on silicon wafer. The interfacial layer plays an important role in reducing the short circuit current, which in turn improves the open circuit voltage and the efficiency of th solar cell. Measurement have been made of the electrical properties of Au-insulation layer-nSi solar cells. It is shown that the efficiency of the cell increase at first with the interfacial layer thickness.