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Serial Changes of Heat Shock Protein 70 and Interleukin-8 in Burn Blister Fluid
( Kicheol Yoo ),( Kang Yeol Suh ),( Gi Hun Choi ),( In-suk Kwak ),( Dong Kook Seo ),( Dohern Kym ),( Hyeon Yoon ),( Yong Se Cho ),( Hye One Kim ) 대한피부과학회 2017 Annals of Dermatology Vol.29 No.2
Background: It has been reported that heat shock protein 70 (HSP70) and interleukin-8 (IL-8) play an important role in cells during the wound healing process. However, there has been no report on the effect of HSP70 and IL-8 on the blisters of burn patients. Objective: This study aimed to evaluate the serial quantitative changes of HSP70 and IL-8 in burn blisters. Methods: Twenty-five burn patients were included, for a total of 36 cases: twenty cases on the first day, six cases on the sec-ond, five cases on the third, three cases on the fourth, and two cases on the fifth. A correlation analysis was performed to de-termine the relationship between the concentration of HSP70 and IL-8 and the length of the treatment period. Results: The HSP70 concentration was the highest on the first day, after which it decreased down to near zero. Most HSP70 was generated during the first 12 hours after the burn accident. There was no correlation between the concen-tration of HSP70 on the first day and the length of the treat-ment period. No measurable concentration of IL-8 was de-tected before 5 hours, but the concentration started to in-crease after 11 hours. The peak value was measured on the fourth day. Conclusion: While HSP70 increased in the first few hours and decreased afterwards, IL-8 was produced after 11 hours and increased afterward in burn blister fluid. These findings provide new evidence on serial changes of in-flammatory mediators in burn blister fluid. (Ann Dermatol 29(2) 194∼199, 2017)
국가 융합 R&D 특성 분석에 관한 연구: 텍스트분석을 중심으로
유기철(KiCheol Yoo),이태희(TaeHee Lee),최상현(SangHyun Choi),이정환(JungHwan Lee) 한국데이타베이스학회 2020 Journal of information technology applications & m Vol.27 No.1
There is a growing interest in convergence. National R & D is also providing various policies and institutional support to promote convergence research. Convergence research, however, does not clearly specify its characteristics at the academic and government levels. This research proceeds with the process of collecting, refining, analyzing, modeling, verifying and visualizing national R & D data through the National Science and Technology Information Service (NTIS). The method is to derive the convergence research characteristics and to derive through text mining, focusing on the unstructured information of national R & D project data. The study confirmed that there was a difference in perception between the definition of converged research and the research site. In order to improve this, the research suggested that convergence among research subjects, collaboration among research topics reflecting various backgrounds and characteristics of researchers, and analysis of characteristics of convergence research using information were suggested in the process of establishing convergence policy.
Chip-package hybrid clock distribution network and DLL for low jitter clock delivery
Chung, Daehyun,Ryu, Chunghyun,Kim, Hyungsoo,Lee, Choonheung,Kim, Jinhan,Bae, Kicheol,Yu, Jiheon,Yoo, Hoijun,Kim, Joungho IEEE 2006 IEEE journal of solid-state circuits Vol.41 No.1
This paper presents a chip-package hybrid clock distribution network and delay-locked loop (DLL) with which to achieve extremely low jitter clock delivery. The proposed hybrid clock distribution network and DLL provide digital noise-free and low-jitter clock signals by utilizing lossless package layer interconnections instead of lossy on-chip global wires with cascaded repeaters. The lossless package layer interconnections become high-frequency waveguides and provide a repeater-free clock distribution network; thus, the clock signal becomes free of on-chip power supply noise. The proposed chip-package hybrid clock scheme has demonstrated a 78-ps peak-to-peak jitter at 500 MHz under a 240-mV on-chip simultaneous switching noise condition versus a conventional clock scheme, which produced a 172-ps peak-to-peak jitter under the same condition. Moreover, the proposed scheme has demonstrated an 80-ps long-term jitter with a 300-mV DC voltage drop test condition, contrasted with the 380-ps long-term jitter of a conventional clock scheme. Finally, the proposed hybrid clock scheme has a confirmed delay of 1.47 ns versus a conventional clock scheme delay of 2.85 ns.