Low Latency Synchronization Scheme Using Prediction and Avoidance of Synchronization Failure in Heterochronous Clock Domains

Sung-Gun Song,Seong-Mo Park,Jeong-Gun Lee,Myeong-Hoon Oh 대한전자공학회 2015 Journal of semiconductor technology and science Vol.15 No.2

For the performance-efficient integration of IPs on an SoC utilizing heterochronous multi-clock domains, we propose a synchronization scheme that causes low latency overhead when data are crossing clock boundaries. The proposed synchronization scheme is composed of a clock predictor and a synchronizer. The clock predictor of a sender clock domain produces a predicted clock that is used in a receiver clock domain to detect possible synchronization failures in advance. When the possible synchronization failures are detected, a synchronizer at the receiver delays data-capture times to avoid the possible synchronization failures. From the simulation of the proposed scheme through SPICE modeling using a Chartered 0.18 mm CMOS process, we verified the functionalities and timing behavior of the clock predictor and the synchronizer. The simulation results show that the clock predictor produces a predicted clock before a synchronization failure, and the synchronizer samples data correctly using the predicted clock.

Low Latency Synchronization Scheme Using Prediction and Avoidance of Synchronization Failure in Heterochronous Clock Domains

Song, Sung-Gun,Park, Seong-Mo,Lee, Jeong-Gun,Oh, Myeong-Hoon The Institute of Electronics and Information Engin 2015 Journal of semiconductor technology and science Vol.15 No.2

For the performance-efficient integration of IPs on an SoC utilizing heterochronous multi-clock domains, we propose a synchronization scheme that causes low latency overhead when data are crossing clock boundaries. The proposed synchronization scheme is composed of a clock predictor and a synchronizer. The clock predictor of a sender clock domain produces a predicted clock that is used in a receiver clock domain to detect possible synchronization failures in advance. When the possible synchronization failures are detected, a synchronizer at the receiver delays data-capture times to avoid the possible synchronization failures. From the simulation of the proposed scheme through SPICE modeling using a Chartered $0.18{\mu}m$ CMOS process, we verified the functionalities and timing behavior of the clock predictor and the synchronizer. The simulation results show that the clock predictor produces a predicted clock before a synchronization failure, and the synchronizer samples data correctly using the predicted clock.

실내측위를 위한 새로운 클락 동기 방안

이영규,양성훈,이승우,이창복,김영범,최성수,Lee, Young-Kyu,Yang, Sung-Hoon,Lee, Seong-Woo,Lee, Chang-Bok,Kim, Young-Beom,Choe, Seong-Su 한국통신학회 2007 韓國通信學會論文誌 Vol.32 No.3A

클락 동기는 실내 측위를 위한 실내 동기망을 구축하는데 있어서 가장 기본적으로 고려해야할 요소 중 하나이다. 본 논문에서는 하드웨어의 복잡성 및 동기에 필요한 데이터 오버헤드를 줄이기 위해 타임스탬프를 사용하지 않고 클락을 동기 시키기 위한 새로운 알고리즘에 대해서 논한다. 또한 동기 성능에 큰 영향을 미치는 주파수 드리프트를 보상해 주기 위한 알고리즘에 대해서도 기술한다. 제안한 동기 알고리즘을 사용한 동기 성능에 대한 평가는 모의실험을 통한 MTIE(Maximum Time Interval Error) 값을 고찰함으로써 이루어졌다. 모의실험에 있어서 실제적인 오실레이터에 대한 주파수 드리프트 값을 사용하였다. 모의실험 결과 1 초의 동기 간격에 1 ns 분해능을 갖고 주 클락과 종속 클락에 TCXO를 사용하면 10 ns 이하의 동기가 가능함을 고찰하였다. Clock Synchronization is one of the most basic factors to be considered when we implement an indoor synchronization network for indoor positioning. In this paper, we present a new synchronization algorithm which does not employ time stamps in order to reduce the hardware complexity and data overhead. In addition to that, we describe an algorithm that is designed to compensate the frequency drift giving an serious impact on the synchronization performance. The performance evaluation of the proposed algorithm is achieved by investigating MTIE (Maximum Time Interval Error) values through simulations. In the simulations, the frequency drift values of the practical oscillators are used. From the simulation results, it is investigated that we can achieve the synchronization performance under 10 ns when we use 1 second synchronization interval with 1 ns resolution and TCXOs (Tmperature Compensated Cristal Oscillators) both in the master clock and the slave clock.

CDR을 사용한 FPGA 기반 분산 임베디드 시스템의 클록 동기화 구현

송재민,정용배,박영석,Song, Jae-Min,Jung, Yong-Bae,Park, Young-Seak 대한임베디드공학회 2017 대한임베디드공학회논문지 Vol.12 No.4

Time synchronization between distributed embedded systems in the Real Time Locating System (RTLS) based on Time Difference of Arrival (TDOA) is one of the most important factors to consider in system design. Clock jitter error between each system causes many difficulties in maintaining such a time synchronization. In this paper, we implemented a system to synchronize clocks between FPGA based distributed embedded systems using the recovery clock of CDR (clock data recovery) used in high speed serial communication to solve the clock jitter error problem. It is experimentally confirmed that the cumulative time error that occurs when the synchronization is not performed through the synchronization logic using the CDR recovery clock can be completely eliminated.

SBAS SIGNAL SYNCHRONIZATION

Gangho Kim,Doyoon Kim,Taikjin Lee,Changdon Kee 한국항해항만학회 2006 한국항해항만학회 학술대회논문집 Vol.1 No.-

In general DGPS system, the correction message is transferred to users by wireless modem. To cover wide area, many DGPS station should be needed. And DGPS users must have a wireless modem that is not necessary in standalone GPS. But SBAS users don’t need a wireless modem to receive DGPS corrections because SBAS correction message is transmitted from the GEO satellite by L1 frequency band. SBAS signal is generated in the GUS(Geo Uplink Subsystem) and uplink to the GEO satellite. This uplink transmission process causes two problems that are not existed in GPS. The one is a time delay in the uplink signal. The other is an ionospheric problem on uplink signal, code delay and carrier phase advance. These two problems cause ranging error to user. Another critical ranging error factor is clock synchronization. SBAS reference clock must be synchronized with GPS clock for an accurate ranging service. The time delay can be removed by close loop control. We propose uplink ionospheric error correcting algorithm for C/A code and carrier. As a result, the ranging accuracy increased high. To synchronize SBAS reference clock with GPS clock, I reviewed synchronization algorithm. And I modified it because the algorithm didn’t consider doppler that caused by satellites’ dynamics. SBAS reference clock synchronized with GPS clock in high accuracy by modified algorithm. We think that this paper will contribute to basic research for constructing satellite based DGPS system.

무선 센서 망에서 주기적인 송수신 모듈 활성화를 위한 클락 동기

김승목(Seung-mok Kim),박태근(Tae-keun Park) 한국멀티미디어학회 2007 멀티미디어학회논문지 Vol.10 No.3

제한된 전원으로 동작해야 하는 센서 노드의 수명 연장을 위하여, 에너지 효율적인 센서 노드의 동작에 대한 많은 연구가 진행되었다. 그들 중에는 주기적으로 무선 송수신 모듈을 활성화 / 비활성화 하면서 정보 전달을 위하여 인접 노드가 깨어나는 시점에 대한 정보를 필요로 하는 기법들이 존재한다. 클락 동기는 이러한 기법들에서 무선 송수신 모듈의 활성화 / 비활성화 스케줄링을 위하여 필수적인 요소이다. 본 논문에서는 센서 망에서 전역 클락 동기를 위하여 제안된 비동기 평균 알고리즘을 기반으로 주기적인 무선 송수신 모듈 활성화 / 비활성화 기법에서의 클락 동기 방법을 제안한다. 구체적으로 본 논문은 (1) 초기 자율적인 망 구성 시점에 필요한 신속한 클락 동기 방법과 (2) 에너지 소모를 최소화한 주기적인 클락 동기 방법 및 (3) 두 가지 동기 방법들 간의 전환 시점 판단 방법을 제안한다. 시뮬레이션을 통하여 제안한 방법의 클락 오차 범위와 교환되는 메시지 수를 분석한다. One of the major issues in recent researches on wireless sensor networks is to reduce energy consumption of sensor nodes operating with limited battery power, in order to lengthen their lifespan. Among the researches, we are interested in the schemes in which a sensor node periodically turns on and off its radio and requires information on the time when its neighbors will wake up (or tum on). Clock synchronization is essential for wakeup scheduling in such schemes. This paper proposes three methods based on the asynchronous averaging algorithm for clock synchronization in sensor nodes which periodically wake up: (1) a fast clock synchronization method during an initial network construction period, (2) a periodic clock synchronization method for saving energy consumption, and (3) a decision method for switching the operation mode of sensor nodes between the two clock synchronization methods. Through simulation, we analyze maximum clock difference and the number of messages required for clock synchronization.

위상차 클럭 기반 NoC 용 동기회로 설계

김강철(Kang-Chul Kim),Jiang Chong 한국전자통신학회 2015 한국전자통신학회 논문지 Vol.10 No.10

NoC는 SoC의 IP 코어들 사이에서 통신하는 시스템으로 기존의 버스 시스템이나 크로스바 상호연결 시스템보다 월등히 향상된 성능을 제공한다. 그러나 NoC의 송신부와 수신부 사이에서 데이터 이동 시에 송신부와 수신부사이에 발생하는 불안정 상태(metastability)는 극복하기 위하여 동기회로가 필요하다. 본 논문에서는 신호 영역발생기, 선택 신호 발생기와 데이터 버퍼로 구성된 새로운 위상차 동기회로를 설계하였다. 불안정 상태가 없는 선택구간을 구하기 위하여 전송된 클럭을 지연하는 회로가 사용되며, 전송클럭과 지역 클럭을 비교하여 선택신호를 발생한다. 제안된 위상차 동기회로는 선택신호 값에 의하여 지역클럭의 상승 또는 하강 모서리 중의 하나를 선택하여 불안정 상태를 제거한다. 모의실험 결과는 제안된 위상차 동기회로가 전송된 클럭과 지역 클럭의 어떤 위상차에서도 잘 동작하는 것을 보여 주었다. Network on a chip(NoC) is a communication subsystem between intellectual property(IP) cores in a SoC and improves high performance in the scalability and the power efficiency compared with conventional buses and crossbar switches. NoC needs a synchronizer to overcome the metastability problem between data links. This paper presents a new mesochronous synchronizer(MS) which is composed of selection window generator, selection signal generator, and data buffer. A delay line circuit is used to build selection window in selection window generator based on the delayed clock cycle of transmitted clock and the transmitted clock is compared with local clock to generate a selection signal in the SW(selection window). This MS gets rid of the restriction of metastability by choosing a rising edge or a falling edge of local clock according to the value of selection signal. The simulation results show that the proposed MS operates correctly for all phase differences between a transmitted clock and a local clock.

Mesochronous Clock Based Synchronizer Design for NoC

김강철,Chong Jiang 한국전자통신학회 2015 한국전자통신학회 논문지 Vol.10 No.10

Network on a chip(NoC) is a communication subsystem between intellectual property(IP) cores in a SoC and improves high performance in the scalability and the power efficiency compared with conventional buses and crossbar switches. NoC needs a synchronizer to overcome the metastability problem between data links. This paper presents a new mesochronous synchronizer(MS) which is composed of selection window generator, selection signal generator, and data buffer. A delay line circuit is used to build selection window in selection window generator based on the delayed clock cycle of transmitted clock and the transmitted clock is compared with local clock to generate a selection signal in the SW(selection window). This MS gets rid of the restriction of metastability by choosing a rising edge or a falling edge of local clock according to the value of selection signal. The simulation results show that the proposed MS operates correctly for all phase differences between a transmitted clock and a local clock.

무선 네트워크 제어 시스템을 위한 클럭 동기화 메커니즘

트렁홉도(Trong-Hop Do),전문길(Wenji Quan),유명식(Myungsik Yoo) 한국통신학회 2013 韓國通信學會論文誌 Vol.38 No.7B

최근 무선 네트워크 기술이 많이 발전됨에 따라 많은 단말과 애플리케이션들은 무선 네트워크를 기반으로 연구되고 있다. 무선 네트워크는 유선 네트워크에 비해 편의성, 유동성, 확장성과 저렴한 가격으로 인하여 많이 사용되고 있지만, 안정성이 떨어지므로 실시간 제어시스템에서의 적용은 제한적이다. 무선 제어시스템에 있어서 가장 중요한 것은 클럭 동기화이다. 비록 기존 유선 네트워크와 무선 네트워크에서 많은 동기화 기법들이 제안 되었지만, 이러한 기법들은 무선 제어 시스템에 직접적으로 적용하기에는 부적절하다. 이에 본 논문에서는 무선 제어 시스템에서의 동기화 문제를 제기하고, 무선 네트워크의 특성들을 이용하여 클럭 동기화 기법을 제안하였다. 이와 더불어 제안 알고리즘의 성능 분석을 위한 모의실험을 수행하였고, 기존 동기화 기법과 제안한 기법을 패킷 손실과 패킷 손실을 제외한 환경에서 비교 분석하였다. Wireless network has been used in many applications due to its advantages such as convenience, mobility, productivity, easy deployment, easy expandability and low cost. When it comes to stability, wireless network still shows its limitation which makes it difficult to be used for real-time control system. One of the first problems of using wireless network for control system is clock synchronization. There have been synchronization schemes proposed for wired networked control system as well as wireless network. But these should not be applied directly in wireless network control system. In this paper, we point out the importance of clock synchronization in wireless network control system. Then based on the characteristic of wireless networked control system, we propose a clock synchronization scheme for it. Furthermore, we simulate our scheme and compare with previous synchronization scheme in wired and wireless environments.

EtherCAT 분산 시계 기반 서보 드라이브의 위치 동기 성능향상에 관한 연구

강동구,이정훈 한국기계기술학회 2022 한국기계기술학회지 Vol.24 No.6

This paper proposes a method to improve the position control synchronization performance by synchronizing the controller operation between servo drives based on the synchronization signal of the EtherCAT(Ethernet for Control Automation Technology)distributed clock. In order to synchronize the operation of the controller between the servo drives, the phase of the operating frequency of the PWM(Pulse Width Modulation) module for motor control was synchronized based on the synchronization signal. At this time, the operation sequence of the current, speed, and position controller of the servo drive operating based on the PWM operating frequency was rearranged. Therefore, the servo drives on the network run the same controller at the same time. And the time at which the master's command is reflected to the drive's controller and the time at which the drive's status information is acquired coincided among the drives. After establishing an experimental environment in which servo drives are arranged in the EthercCAT network system, we verified that the position synchronization performance between servo drives applying the proposed method is improved.