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Cho, Yongbeom,Cho, Seongjae,Park, Byung-Gook,Harris, James S. Jr. The Institute of Electronics and Information Engin 2017 Journal of semiconductor technology and science Vol.17 No.5
Ge is on increasing demand in the advanced Si-compatible high-speed integrated circuits due to its high carrier mobilities. In particular, its hole mobility is much higher than those of other group-IV and III-V compound semiconductor materials. At the same time, Ge has the local minimum at the ${\Gamma}$ valley, which enables the utilization for optical applications. The fact that Ge becomes a direct-bandgap semiconductor material by applying tensile strain can be a good merit in obtaining higher spontaneous radiation probability. However, engineering the electronic structure of Ge by external mechanical stress through stressors with different thermal expansion coefficients might require a complicated set of processes. Efforts were made to turn it into a direct-bandgap one by incorporating Sn. Carrier mobilities are further enhanced when Sn is substitutionally incorporated into the Ge matrix. Thus, advantageous features are expected in improving both optical and electrical performances. Furthermore, the small bandgap energy and bandgap tunability make $Ge_{1-x}Sn_x$ alloy a promising material for components making up the optical interconnect on Si platform including optical source of near-infrared wavelength. In this work, we study the electrical and optical characteristics of $Ge_{1-x}Sn_x$ alloy as a function of Sn content. To achieve this goal, ab initio calculations of energy-band structures of $Ge_{1-x}Sn_x$ with different Sn fractions have been carried out based on linearized augmented plane wave (LAPW) method with modified Becke-Johnson potential model for more accurate bandgap energy. Then, a novel coding method has been adopted for more reliable overall band structures. The minimum Sn content required for direct- and indirect-bandgap material transition of $Ge_{1-x}Sn_x$, electrical and optical energy bandgaps to investigate the bandgap tunability, as well as effective masses, have been extracted as a function of Sn content. The transition point was found to be 6.9% and succinct reductions of effective masses of electron and hole have been confirmed.
CHO, Seongjae,LEE, Jung Hoon,LEE, Gil Sung,LEE, Jong Duk,SHIN, Hyungcheol,PARK, Byung-Gook The Institute of Electronics, Information and Comm 2009 IEICE transactions on electronics Vol.92 No.5
<P>Recently, various types of 3-D nonvolatile memory (NVM) devices have been researched to improve the integration density [1]-[3]. The NVM device of pillar structure can be considered as one of the candidates [4], [5]. When this is applied to a NAND flash memory array, bottom end of the device channel is connected to the bulk silicon. In this case, the current in vertical direction varies depending on the thickness of silicon channel. When the channel is thick, the difference of saturation current levels between on/off states of individual device is more obvious. On the other hand, when the channel is thin, the on/off current increases simultaneously whereas the saturation currents do not differ very much. The reason is that the channel potential barrier seen by drain electrons is lowered by read voltage on the opposite sidewall control gate. This phenomenon that can occur in 3-D structure devices due to proximity can be called gate-induced barrier lowering (GIBL). In this work, the dependence of GIBL on silicon channel thickness is investigated, which will be the criteria in the implementation of reliable ultra-small NVM devices.</P>
Design and optimization of two-bit double-gate nonvolatile memory cell for highly reliable operation
Cho, Seongjae,Park, Il Han,Kim, Tae Hun,Sim, Jae Sung,Song, Ki-Whan,Lee, Jong Duk,Shin, Hyungcheol,Park, Byung-Gook IEEE 2006 IEEE TRANSACTIONS ON NANOTECHNOLOGY Vol.5 No.3
In this paper, characterization and optimization have been performed on the 2-b floating-gate-type nonvolatile memory (NVM) cell based on a double-gate (DG) MOSFET structure using two-dimensional numerical simulation. The thickness and the difference of charge amount between programmed and erased states are found to be the crucial factors that put the NVM cell operation under optimum condition. Under fairly good conditions, the silicon thickness can reach below 30 nm while suppressing the read disturbance level within 1 V. With these results, operating schemes are investigated for both NAND - and NOR-type memory cells. This paper is based on simulation works which can give a reasonable intuition in flash memory operation. Although we adopted a floating-gate-type device since the exact modeling of Si<SUB>3</SUB>N<SUB>4</SUB> used for the storage node is absent in the current numerical simulator, this helps to predict the operation of an oxide-nitride-oxide dielectric flash memory cell at a good degree.
A More Practical Indicator of MAC Operational Power Efficiency inside Memory-based Synapse Array
Seongjae Cho,Sung-Tae Lee,Soo Min Kim,Hyungcheol Shin 대한전자공학회 2024 Journal of semiconductor technology and science Vol.24 No.1
Recently, existing software-based artificial intelligence technology is being implemented through hardware to improve area and energy efficiencies. Thus, there might be various performance indicators, but power efficiency is an important criterion for evaluating the performance of artificial intelligence chips. Currently, frequently used power efficiency indicators are for all-circuit-based artificial intelligence semiconductor chips, and for the cell-level technology-based artificial intelligence chips that can maximize power efficiency, it is difficult to use the existing indicators as they are. This study presents a practical indicator for evaluating power efficiency when implementing memory cell-based artificial intelligence semiconductor chips. Unlike conventional methodologies, the proposed performance indicators provide a clearer picture of power efficiency changes depending on what type of memory cell is used. Furthermore, the number of multiplicate-and-accumulate (MAC) operations and the number of memory cells cancel each other in the process of deriving the index, which can be a more significant indicator in the memory technology perspective in the sense that it has a greater dependence on the electrical characteristics of the memory cells themselves than on array density.
Seongjae Cho,Il Han Park,Tae Hun Kim,Jung Hoon Lee,Jong Duk Lee,Hyungcheol Shin,Byung-Gook Park 대한전자공학회 2005 Journal of semiconductor technology and science Vol.5 No.3
Recently, a novel multi-bit nonvolatile memory based on double gate (DG) MOSFET is proposed to overcome the short channel effects and to increase the memory density. We need more complex voltage schemes for DG MOSFET devices. In view of peripheral circuits driving memory cells, one should consider various voltage sources used for several operations. It is one of the key issues to minimize the number of voltage sources. This criterion needs more caution in considering a DG nonvolatile memory cell that inevitably requires more number of events for voltage sources. Therefore figuring out the permissible range of operating bias should be preceded for reliable operation. We found that reliable operation largely depends on the depletion conditions of the silicon channel according to charge amount stored in the floating gates and the negative control gate voltages applied for read operation. We used Silvaco Atlas, a 2-D numerical simulation tool as the device simulator.
Seongjae Cho,Il Han Park,Jung Hoon Lee,Yun Kim,Hyungcheol Shin,Byung-Gook Park 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7
In this work, analytical modeling of channel potential and surface charge density for gate-all-around (GAA) and silicon nanowire (SNW) MOSFET devices. It is postulated that the silicon channel is undoped or very lightly doped under arbitrary surface potential. Based on the radial potential functions, channel and center potentials are investigated with variation on silicon channel radius and surface potentials. Furthermore, surface charge density is induced from the resultant analytic function. The modelings have been performed by fully solving the cylindrical Poisson’s equation without consideration of quantum effects, and the results are graphitized by MATLAB, a mathematical tool.
Seongjae Cho,Shinichi O’uchi,Kazuhiko Endo,Sang Wan Kim,Younghwan Son,In Man Kang,Meishoku Masahara,James S. Harris,Byung-Gook Park 대한전자공학회 2010 Journal of semiconductor technology and science Vol.10 No.4
In this work, reliable methodology for device design is presented. Based on this method, the underlap length has been optimized for minimizing the gateinduced drain leakage (GIDL) in a 22-㎚ node 4-terminal (4-T) silicon-on-insulator (SOI) fin-shaped field effect transistor (FinFET) by TCAD simulation. In order to examine the effects of underlap length on GIDL more realistically, doping profile of the source and drain (S/D) junctions, carrier lifetimes, and the parameters for a band-to-band tunneling (BTBT) model have been experimentally extracted from the devices of 90-㎚ channel length as well as pnjunction test element groups (TEGs). It was confirmed that the underlap length should be near 15 ㎚ to suppress GIDL effectively for reliable low standby power (LSTP) operation.