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      • SCOPUSKCI등재SCIE

        Visible light-driven photocatalytic degradation of doxycycline using ZnO/g-C₃N₄/biochar composite in aqueous solution

        Nguyen Van Hung,Bui Thi Minh Nguyet,Nguyen Huu Nghi,Nguyen Minh Luon,Nguyen Ngoc Bich,Le Van Thanh Son,Nguyen Trung Kien,Dao Ngoc Nhiem,Nguyen Thanh Tuoi,Dinh Quang Khieu 대한환경공학회 2024 Environmental Engineering Research Vol.29 No.4

        In the present work, ZnO/g-C₃N₄/biochar was prepared, and it was used for visible-light driven photocatalytic degradation of some colorants (methylene blue, rhodamine B, methyl orange) and some antibiotics (doxycycline, ciprofloxacin, amoxicilline). Biochar was prepared by pyrolysing Phragmites australis biomass. The ZnO/g-C₃N₄/biochar composite was synthesized with the alkaline hydrolysis method. The obtained materials were characterized by X-ray diffraction, scanning electron microscopy, transition electron microscopy, energy dispersive X-ray/elemental mapping, ultraviolet-visible-diffuse reflectance spectroscopy, photoluminescence spectroscopy, nitrogen adsorption/desorption isotherms and X-ray photoelectron spectroscopy. The results show that ZnO nanoparticles with a large surface area are highly dispersed on the g-C₃N₄ particle surface and biochar. The composite exhibits superior photocatalytic degradation ability toward doxycycline, a broad-spectrum antibiotic of the tetracycline compared with individual components (ZnO or g-C₃N₄) and satisfies stability after six treatment cycles. The kinetics and degradation mechanisms of doxycyline were also addressed. In addition, the present catalyst also exhibits the photocatalytic degradation of methylene blue, rhodamine B, methyl orange, ciprofloxacin and amoxicillin in visible-light regions.

      • KCI등재

        Parenchymal-sparing anatomical hepatectomy based on portal ramification of the right anterior section: A prospective multicenter experience with short-term outcomes

        Truong Giang Nguyen,Thanh Khiem Nguyen,Ham Hoi Nguyen,Hong Son Trinh,Tuan Hiep Luong,Minh Trong Nguyen,Van Duy Le,Hai Dang Do,Kieu Hung Nguyen,Van Minh Do,Quang Huy Tran,Cuong Thinh Nguyen 한국간담췌외과학회 2024 Annals of hepato-biliary-pancreatic surgery Vol.28 No.1

        Backgrounds/Aims: Parenchymal-sparing anatomical hepatectomy (Ps–AH) based on portal ramification of the right anterior section (RAS) is a new technique to avoid unnecessarily transecting too much liver parenchyma, especially in cases of major anatomical hepatectomy. Methods: We prospectively assessed 26 patients with primary hepatic malignancies having undergone major Ps–AH based on portal ramification of the RAS from August 2018 to August 2022 (48 months). The perioperative indications, clinical data, intra-operative index, pathological postoperative specimens, postoperative complications, and follow-up results were retrospectively evaluated. Results: Among the 26 patients analyzed, there was just one case that had intrahepatic cholangiocarcinoma The preoperative level of α– Fetoprotein was 25.2 ng/mL. All cases (100%) had Child–Pugh A liver function preoperatively. The ventral/dorsal RAS was preserved in 19 and 7 patients, respectively. The mean surgical margin was 6.2 mm. The mean surgical time was 228.5 minutes, while the mean blood loss was 255 mL. In pathology, 5 cases (19.2%) had microvascular invasion, and in the group of HCC patients, 92% of all cases had moderate or poor tumor differentiation. Six cases (23.1%) of postoperative complications were graded over III according to the Clavien–Dindo system, including in three patients resistant ascites or intra-abdominal abscess that required intervention. Conclusions: Parenchymal-sparing anatomical hepatectomy based on portal ramification of the RAS to achieve R0-resection was safe and effective, with favorable short-term outcomes. This technique can be used widely in clinical practice.

      • The Conversion Algorithm between Double-Base Number System and Floating-Point Number System applied for FIR filter

        Minh Son Nguyen,JongSoo Kim 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7

        To design an integrated 6-bit flash ADC and DSP circuit on SoC using double-base number system (DBNS), this paper proposes new model with partition technique to design the conversion of double-base number to floating-point number unlike other approaches which need ROM architecture. The basic idea of partition technique is to find on the linear approximation of function power of 2 in range of [0, 1). A FIR filter is designed to prove the effectiveness of the new proposed algorithm. The simulation results reveal the proposed design is more attractive than the previous researches in DBNS applications.

      • KCI등재

        Unsteady analysis of a solar air heater with sensible heat storage using 2D finite difference approximation

        Nguyen Minh Phu,Lai Hoai Nam,Nguyen Le Hong Son 대한기계학회 2023 JOURNAL OF MECHANICAL SCIENCE AND TECHNOLOGY Vol.37 No.11

        In this paper, an air collector with sensible heat storage is numerically solved using the finite difference method. The change in temperatures of the glass, airflow, and absorber plate is assumed to be unidirectional. Meanwhile, heat conduction in the storage material is considered in two dimensions. Six storage materials containing brick, granite, slag, limestone, sandstone, and concrete are simulated unsteadily. Numerical techniques, including an implicit method, an upwind scheme, the Thomas algorithm, and the ADI method, are used to solve a system of differential equations describing the collector. The charging and discharging mechanisms are effectively explained by the two-dimensional temperature distribution of the storage material. Results indicate that the charge and discharge periods are up to 16:00 PM and 24:00 PM, respectively, demonstrating an air temperature difference of 4.5 °C for the granite thickness of 5 cm. Granite and slag are suitable storage materials due to their superior thermal properties. The air channel height has a significant effect on the performance of the collector. The air temperature difference doubles when the channel height is reduced from 5 cm to 2 cm.

      • KCI등재후보

        Application of Constraint Algorithm for High Speed A/D Converters

        Minh Son Nguyen,Soo A Yeo,Man-Ho Kim,Jongsoo Kim 한국융합신호처리학회 2008 융합신호처리학회 논문지 (JISPS) Vol.9 No.3

        In the paper, a new Constraint algorithm is proposed to solve the fan-in problem occurred in the encoding circuitry of an ADC. The Flash ADC architecture uses a Double-Base Number System(DBNS). The DBNS has been known to represent the Multidimensional Logarithmic Number System (MDLNS) used for implementing the multiplier accumulator architecture of FIR filter in Digital Signal Processing (DSP) applications. The authors use the DBNS with the base 2 and 3 in designing ADC encoder circuits, which is called as Double Base Integer Encoder(DBIE). A symmetric map is analyzed first, and then asymmetric map is followed to provide addition ready DBNS for DSP circuitry. The simulation results of the DBIE circuits in 6-bit and 8-bit ADC show the effectiveness of the Constraint algorithm with 0.18 CMOS technology. The DBIE yields faster processing speed compared to the speed of Fat Tree Encoder (FAT) circuits by 17% at more power consumption by 39%.

      • SCIESCOPUSKCI등재

        Constraint Algorithm in Double-Base Number System for High Speed A/D Converters

        Nguyen, Minh Son,Kim, Man-Ho,Kim, Jong-Soo The Korean Institute of Electrical Engineers 2008 Journal of Electrical Engineering & Technology Vol.3 No.3

        In the paper, an algorithm called a Constraint algorithm is proposed to solve the fan-in problem occurred in ADC encoding circuits. The Flash ADC architecture uses a double-base number system (DBNS). The DBNS has known to represent the multi-dimensional logarithmic number system (MDLNS) used for implementing the multiplier accumulator architecture of FIR filter in digital signal processing (DSP) applications. The authors use the DBNS with the base 2 and 3 to represent binary output of ADC. A symmetric map is analyzed first, and then asymmetric map is followed to provide addition read DBNS to DSP circuitry. The simulation results are shown for the Double-Base Integer Encoder (DBIE) of the 6-bit ADC to demonstrate an effectiveness of the Constraint algorithm, using $0.18{\mu}\;m$ CMOS technology. The DBIE’s processing speed of the ADC is fast compared to the FAT tree encoder circuit by 0.95 GHz.

      • KCI등재

        First Report on Multidrug-Resistant Methicillin-Resistant Staphylococcus aureus Isolates in Children Admitted to Tertiary Hospitals in Vietnam

        ( Nguyen Thai Son ),( Vu Thi Thu Huong ),( Vu Thi Kim Lien ),( Do Thi Quynh Nga ),( Tran Thi Hai Au ),( Tang Thi Nga ),( Le Nguyen Minh Hoa ),( Tran Quang Binh ) 한국미생물생명공학회(구 한국산업미생물학회) 2019 Journal of microbiology and biotechnology Vol.29 No.9

        The extensive distribution of multidrug-resistant (MDR) methicillin-resistant Staphylococcus aureus (MRSA) poses a threat to healthcare worldwide. This study aimed to investigate the MDR and molecular patterns of MRSA isolates in children admitted to the two biggest tertiary care pediatric hospitals in northern and southern Vietnam. A total of 168 MRSA strains were collected to determine antibiotic susceptibility by minimum inhibitory concentration tests. Antibiotic-resistant genes, pulsed-field gel electrophoresis, staphylococcal cassette chromosome mec (SCCmec) typing, and multilocus sequence typing were used for the molecular characterization of MRSA. Among the total strains, the MDR rate (51.8%) was significantly higher in the northern hospital than in the southern hospital (73% vs. 39%, p < 0.0001). The MDR-MRSA with the highest rates were “ciprofloxacin-erythromycin-gentamicin-tetracyclines” (35.6%), followed by “erythromycin-tetracycline-chloramphenicol” (24.1%), and “ciprofloxacin-erythromycin-gentamicin” (19.5%), showing an accumulative total of 79.3%. The most susceptible antibiotics were rifampicin (100%) and vancomycin (100%), followed by doxycycline (94.0%), meropenem (78.0%), and cefotaxime (75.0%). The SCCmecII strains showed greater resistance to gentamicin, ciprofloxacin, tetracycline, meropenem and cephalosporins compared with the other strains. The SCCmecII strains exhibited the highest rate in the tested genes (aacA/aphD: 55.2%, ermA/B/C: 89.7%, and tetK/M: 82.8%). ST5-SCCmecII was the predominant clone in the northern hospital, whereas SCCmecIVa was more pronounced in the southern hospital. In conclusion, our results raised concerns about the predominant MDR-MRSA strains in the pediatric hospitals in Vietnam. The north-south difference in the antibiotic resistance patterns and genetic structure of MRSA suggests different MRSA origins and various uses of antimicrobial agents between the two regions.

      • SCOPUSKCI등재

        First-Principles Investigation on the Electromechanical Properties of Monolayer 1H Pb-Dichalcogenides

        Nguyen Hoang Linh,Nguyen Minh Son,Tran The Quang,Nguyen Van Hoi,Vuong Thanh,Do Van Truong Materials Research Society of Korea 2023 한국재료학회지 Vol.33 No.5

        This study uses first-principles calculations to investigate the mechanical properties and effect of strain on the electronic properties of the 2D material 1H-PbX<sub>2</sub> (X: S, Se). Firstly, the stability of the 1H Pb-dichalcogenide structures was evaluated using Born's criteria. The obtained results show that the 1H-PbS<sub>2</sub> material possesses the greatest ideal strength of 3.48 N/m, with 3.68 N/m for 1H-PbSe<sub>2</sub> in biaxial strain. In addition, 1H-PbS<sub>2</sub> and 1H-PbSe<sub>2</sub> are direct semiconductors at equilibrium with band gaps of 2.30 eV and 1.90 eV, respectively. The band gap was investigated and remained almost unchanged under the strain ε<sub>xx</sub> but altered significantly at strains ε<sub>yy</sub> and ε<sub>bia</sub>. At the fracture strain in the biaxial direction (19 %), the band gap of 1H-PbS<sub>2</sub> decreases about 60 %, and that of 1H-PbSe<sub>2</sub> decreases about 50 %. 1H-PbS<sub>2</sub> and 1H-PbSe<sub>2</sub> can convert from direct to indirect semiconductor under the strain ε<sub>yy</sub>. Our findings reveal that the two structures have significant potential for application in nanoelectronic devices.

      • KCI등재

        New Multiplication Architecture for DSP Applications

        Nguyen-Minh Son,김종수,최재하 한국융합신호처리학회 2011 융합신호처리학회 논문지 (JISPS) Vol.12 No.2

        he modern digital logic technology does not yet satisfy the speed requirements of real-time DSP circuits due to synchronized operation of multiplication and accumulation. This operation degrades DSP performance. Therefore, the double-base number system (DBNS) has emerged in DSP system as an alternative methodology because of fast multiplication and hardware simplicity. In this paper, authors propose a novel multiplication architecture. One operand is an output of a flash analog-to-digital converter (ADC) in DBNS format, while the other operand is a coefficient in the IEEE standard floating-point number format. The DBNS digital output from ADC is produced through a new double base number encoder (DBNE). The multiplied output is in the format of the IEEE standard floating-point number (FPNS). The proposed circuits process multiplication and conversion together. Compared to a typical multiplier that uses the FPNS, the proposed multiplier also consumes 45% less gates, and 44% faster than the FPNS multiplier on Spartan-3 FPGA board. The design is verified with FIR filter applications.

      • KCI등재

        New Multiplier for a Double-Base Number System Linked to a Flash ADC

        Minh Son Nguyen,Insoo Kim,Kyusun Choi,Jaehyun Lim,Wonho Choi,Jongsoo Kim 한국전자통신연구원 2012 ETRI Journal Vol.34 No.2

        The double-base number system has been used in digital signal processing systems for over a decade because of its fast inner product operation and low hardware complexity. This letter proposes an innovative multiplier architecture using hybrid operands. The multiplier can easily be linked to flash analog-to-digital converters or digital systems through a double-base number encoder (DBNE) for realtime signal processing. The design of the DBNE and the multiplier enable faster digital signal processing and require less hardware resources compared to the binary processing method.

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