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Charge Controlled Meminductor Emulator
Sah, Maheshwar Pd.,Budhathoki, Ram Kaji,Yang, Changju,Kim, Hyongsuk The Institute of Electronics and Information Engin 2014 Journal of semiconductor technology and science Vol.14 No.6
Emulations of memristor-family elements are very important, since their physical realizations are very difficult to achieve with recent technologies. Although some previous studies succeeded in designing memristor and memcapacitor emulators, no significant contribution towards meminductor emulator has been presented so far. The implementation of a meminductor emulator is very important, since real meminductors are not expected to appear in near future. We designed the first meminductor emulator whose inductance can be varied by an external current source without employing any memrisitve system. The principle of our architecture and its feasibility have been verified using SPICE simulation.
Charge Controlled Meminductor Emulator
Maheshwar Pd. Sah,Ram Kaji Budhathoki,Changju Yang,Hyongsuk Kim 대한전자공학회 2014 Journal of semiconductor technology and science Vol.14 No.6
Emulations of memristor-family elements are very important, since their physical realizations are very difficult to achieve with recent technologies. Although some previous studies succeeded in designing memristor and memcapacitor emulators, no significant contribution towards meminductor emulator has been presented so far. The implementation of a meminductor emulator is very important, since real meminductors are not expected to appear in near future. We designed the first meminductor emulator whose inductance can be varied by an external current source without employing any memrisitve system. The principle of our architecture and its feasibility have been verified using SPICE simulation.
A Feed forward Differential Architecture for the Analog PRML Viterbi Decoder
Maheshwar Pd. Sah(마헤스워 사),Changju Yang(양창주),Hyongsuk Kim(김형석) 제어로봇시스템학회 2010 제어로봇시스템학회 합동학술대회 논문집 Vol.2010 No.12
In this paper, an analog parallel processing circuit in the form of feed forward differential architecture is proposed to implement on analog PRML Viterbi decoder. It is based on the idea that the decoding of PRML is done mainly with the information of the first several number of stages. Several benefits including higher speed, no path memory, no trace back unit and no A/D converter are required for the decoding of the signals. Most of the conventional analog parallel processing-based PRML decoders are differential architecture with the feedback, where states are changed depending on the previous decoded data. The architecture used in this paper is without feedback, where error metric accumulation is allowed to start from odd and even input of subtrellis. It is simpler than that of the conventional analog parallel processing structure with similar decoding performance. The feature of proposed architecture is investigated through simulation results.
Memristor Circuit for Artificial Synaptic Multiplication
Maheshwar Pd. Sah(마헤스워 사),Changju Yang(양창주),이청호,Hyongsuk Kim(김형석) 제어로봇시스템학회 2011 제어로봇시스템학회 각 지부별 자료집 Vol.2011 No.7
A memristor circuit is proposed to synaptic multiplication of artificial neural networks by using ohms law v = M(q) x i. The weight and synaptic processing can be performed positively or negatively through a share input terminal. Several benefits like compact integration, lower power consumption and analog processing is applicable in the circuit. The simulations of the proposed circuit are analyzed with Hewlett-Packard (HP) TiO₂ memristor model.
Sah, Maheshwar Pd,Hyongsuk Kim,Chua, Leon O. IEEE 2014 IEEE circuits and systems magazine Vol.14 No.1
<P>This exposition shows that the potassium ion-channels and the sodium ion-channels that are distributed over the entire length of the axons of our neurons are in fact locally-active memristors. In particular, they exhibit all of the fingerprints of memristors, including the characteristic pinched hysteresis Lissajous figures in the voltage-current plane, whose loop areas shrink as the frequency of the periodic excitation signal increases. Moreover, the pinched hysteresis loops for the potassium ion-channel memristor, and the sodium ion-channel memristor, from the Hodgkin-Huxley axon circuit model are unique for each periodic excitation signal. An in-depth circuit-theoretic analysis and characterizations of these two classic biological memristors are presented via their small-signal memristive equivalent circuits, their frequency response, and their Nyquist plots. Just as the Hodgkin-Huxley circuit model has stood the test of time, its constituent potassium ion-channel and sodium ion-channel memristors are destined to be classic examples of locally-active memristors in future textbooks on circuit theory and bio-physics.</P>
Memcapacitor Emulator with Off-the-Shelf Devices
Maheshwar Pd. Sah(마헤스워 샤파라),Ramkaji Budhathoki(람 카지 부다토기),Changju Yang(양창주),Hyeon Cheol(최현철),Hyongsuk Kim(김형석) 제어로봇시스템학회 2013 제어로봇시스템학회 각 지부별 자료집 Vol.2013 No.12
We built a memcapacitor emulator with off-the-shelf electronic devices. The memcapacitor is an element whose capacitance can be altered with external current or voltage. The implementation of the emulator is very important since commercial versions are not yet available. The proposed memcapacitor emulator has a simple dedicated memcapacitor architecture that does not require a mutator. It is the first memcapacitor emulator implemented with commercially available devices. The operation as a memcapacitor has been proven via both breadboard experiments and PSPICE simulations.
A Generic Model of Memristors With Parasitic Components
Sah, Maheshwar Pd.,Yang, Changju,Kim, Hyongsuk,Muthuswamy, Bharathwaj,Jevtic, Jovan,Chua, Leon IEEE 2015 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 1 R Vol.62 No.3
<P>In this paper, a generic model of memristive systems, which can emulate the behavior of real memristive devices is proposed. Non-ideal pinched hysteresis loops are sometimes observed in real memristive devices. For example, the hysteresis loops may deviate from the origin over a broad range of amplitude <TEX>$A$</TEX> and frequency <TEX>$f$</TEX> of the input signal. This deviation from the ideal case is often caused by parasitic circuit elements exhibited by real memristive devices. In this paper, we propose a generic memristive circuit model by adding four parasitic circuit elements, namely, a small capacitance, a small inductance, a small DC current source, and a small DC voltage source, to the memristive device. The adequacy of this model is verified experimentally and numerically with two thermistors (NTC and PTC) memristors.</P>
Max-based Analog Absolute Circuits with Small Error
마헤스워사(Maheshwar pd.sah),임해평(Lin, Hai-Ping),양창주(Yang, Chang-Ju),이준호(Lee, Jun-Ho),김형석(Kim, Hyong-Suk) 한국산학기술학회 2009 한국산학기술학회논문지 Vol.10 No.2
통신시스템에서의 에러의 처리는 매우 중요한 문제로서 비터비 디코더와 같은 에러처리를 위해서 주로 절대값으로 표현하기 때문에 아날로그 절대값 회로가 자주 필요하게 된다. 이 논문에서는 절대값을 정확하게 계산할 수 있는 아날로그 절대값 회로를 제안하였다. 제안한 절대값 회로에는 부호가 반대인 두 신호들을 만든 다음, 이 신호들을 아날로그MAX회로에 인가하여 둘 중 최대값을 출력하게 하는 방법이다. 이 구조를 회로로 구현하기 위해서는 두 개의 입력 신호를 반대방향으로 차를 구하여, 크기는 같고 부호가 다른 두 개의 신호를 만든 다음 이들을 MAX회로의 입력으로 사용하는 회로를 설계하였다. 본 논문에서는 제안한 회로를 Hspice를 이용하여 시뮬레이션을 수행했으며, 그 결과를 제시하였다. Error is the major problem in communication system. Absolute circuit is one of the most important building blocks to implement for the error measurement in communication system as well as in analog circuit design. The main goal of this paper is to design a circuit with high accuracy and minimum error performance. In this paper, a new current mode absolute circuit is implemented to calculate the absolute value of two signals. This new design shows enhanced performance and low distortion over the previous implementation. The proposed circuit is simulated using Hspice and implemented in analog viterbi decoder. It is very suitable for implementing in error calculation for the large scale integrated circuit. Hspice simulation results of previous and new one circuit are reported.