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蔡相勳 호서대학교 공업기술연구소 2000 工業技術硏究所論文集 Vol.19 No.-
A CMOS transceiver ASIC for the 155.52 Mbpa STM-1 digital communication system etc., was designed. It transmits 155.52 Mbps serial data transformed from 19.44 Mbps parallel data. 155.52 MHz clock for synchronization of data is generated using reference 19.44 MHz clock by an analog PLL while parallel to serial data conversion is done by a digital circuit. The transceiver receives 155.52 Mbps serial data ad transforms to 19.44 Mbps parallel data. 155.52 MHz clock for synchronization of data is recovered using 155.52 Mbps input data by an analog PLL while serial to parallel data conversion is done by a digital circuit. Circuit simulations confirm that PLL locking and data conversion are accomplished successfully. The area of the designed ASIC chip is 3.0×3.8 mm2 using 0.6 μm process and the estimated power consumption of the chip are less than 300 mW with a single 5 V supply, respectively.
채상훈 湖西大學校工業技術硏究所 2003 工業技術硏究所論文集 Vol.22 No.-
This paper has been studied on wafer cleaning and photoresist striping in semiconductor or LCD fabrication processes using ozone solved deionized water. For the purpose of this study, we have developed high concentration ozone generating system and high contact ratio ozone solving system to get high efficiency DIO_(3). Through this study, we obtained 11% ozone gas concentration, 99.5% of ozone efficiency and maximum 139.1 ppm㎎/L)of solubility in deionized water.
디지털 방식을 사용한 버스트 모드 광 송신기의 온도보상에 관한 연구
채상훈 湖西大學校 工業技術硏究所 2005 工業技術硏究所論文集 Vol.24 No.-
A temperature compensation block was fabricated and evaluated to use in burst mode fiber optic modules which convert the electrical burst mode data to optical signal through laser diode. To obtain stable temperature compensation characteristics we used a microprocessor instead of a analog circuit block as the temperature compensation block. Using this method we can get more effective controllability in alternative temperature changing and long time using condition.
광통신 모듈용 155.52 Mbps 리시버 ASIC의 설계
蔡相勳 湖西大學校工業技術硏究所 1999 工業技術硏究所論文集 Vol.18 No.-
A 155.52 Mbps receiver ASIC for fiber-optic modules has been designed and fabricated with 0.65 ㎛ CMOS technology. The designed ASIC has a limit amplifier circuit for 155.52 Mbps data reshaping and a PLL circuit for 155.52 MHz clock extraction. The designed circuit has a frequency self-generating circuit and a LOS monitoring circuit for properly operating with 155.52 MHz clock frequency in case of the data loss due to transmission line open or data from 1 mV to 1 V input voltage condition, and stably generates 155.52 MHz clock on any data input condition.
Verilog-A를 이용한 PLL회로 설계 및 시뮬레이션
채상훈 湖西大學校 工業技術硏究所 2002 工業技術硏究所論文集 Vol.21 No.-
This paper introduces to design analog circuits with Verilog-A. It is a tool for design and simulation analog ICs in behavioral level. Verilog-A has been already established standard and used to IP development in USA. We have proven the possibility of Verilog-A by compared with measurement data of a fabricated 235MHz PLL circuit. This paper also describes another advantage of Verilog-A.
공기중의 Radon 방사능 측정에 의한 서울 대기의 혼합높이 결정
김의훈,김필수,김채옥,이건상,권기덕 漢陽大學校 環境科學硏究所 1985 環境科學論文集 Vol.6 No.-
서울 대기의 혼합높이를 1984년1월부터 4월 사이에 지표고도에서 측정한 ??으로부터 결정하였다. ?? 농도로부터 상당혼합높이를 계산하기 위하여 한 수식 모델을 개발하였다. 이로부터 계산한 상당혼합높이는 늦은 오후에 최고 및 밤 또는 이른 아침에 최저값을 가지며 수 십 미터에서 1킬로미터 또는 그 이상의 높이를 보이는 일변화를 나타냈다. 평균혼합높이는 겨울이 낮았다. 이와 같은 변화는 대기의 안정도, 일조시간, 기온 등 대기의 인자와 밀접한 관계가 있었다. The mixing heigt of the atmosphere in Seoul was determined from the measurement of ?? concentration in air at ground level for January 1984 to April 1984. In order to calculate the equivalent mixing height from ?? concentration, a mathematical model was developed. The equivalent mixing heights calculated from this model showed diurnal variation with the highest values in the late afternoon and the lowest during night hours or early morning ranging from several tens to one thousand meters or more. The average heights represented lower values in the winter. These variations were closely related to the atmospheric factors, such as atmospheric stability, daytime hour, and temperature, etc.
광통신 모듈용 155.52 Mbps CMOS 리시버제작 및 구현
이길재,채상훈 호서대학교 반도체제조장비국산화연구센터 2000 학술대회 자료집 Vol.2000 No.1
STM-1 체계의 광통신 수신부 광모듈에 내장하기 위한 155.52 Mbps 리시버 ASIC을 0.65 ㎛ 실리콘 CMOS 기술을 이용하여 설계 제작하였다. 제작된 ASIC은 155.52 Mbps 데이터신호 재정형을 위한 제한 증폭기와 155.52 MHz 클럭을 추출하기 위한 클럭 추출 회로를 주축으로 구성되어 있다. 또한 이 리시버는 전원이 켜지는 초기 동작 상태에서나 동작 도중 데이터신호가 입력되지 않더라도 155.52 MHz 부근의 클럭주파수를 유지하여 항상 안정된 동작을 할 수 있게 하기 위한 수렴 보조 회로 및 LOS 감지 회로도 내장하고 있다. 측정 결과 설계된 리시버는 1 mV - 1 V의 넓은 입력 전압에 걸쳐 데이터 재정형이 이루어지며, 155.52 MHz의 안정된 클럭을 추출하고 있음을 알 수 있었다.
채상훈(Sang-Hoon Chai),이만섭(Man-Sup Lee),조영창(Young-Chang Cho) 한국조명·전기설비학회 2011 한국조명·전기설비학회 학술대회논문집 Vol.2011 No.11
A novel efficient group dimming technique is presented. This technique can be applied not only group dimming control of fluorescent or LED lights but also group control of other electrical equipments like heater or motor systems. Some simple technique was used for group dimming control of lamps instead of using communication. To transport control signal for group dimming of lighting system from switch to lamps near 0 crossing point(0~±16V) of AC 220V power signal was transformed to special shape.
High-Current Trench Gate DMOSFET Incorporating Current Sensing FET for Motor Driver Applications
Kim, Sang-Gi,Won, Jong-Il,Koo, Jin-Gun,Yang, Yil-Suk,Park, Jong-Moon,Park, Hoon-Soo,Chai, Sang-Hoon The Korean Institute of Electrical and Electronic 2016 Transactions on Electrical and Electronic Material Vol.17 No.5
In this paper, a low on-resistance and high current driving capability trench gate power metal-oxide-semiconductor field-effect transistor (MOSFET) incorporating a current sensing feature is proposed and evaluated. In order to realize higher cell density, higher current driving capability, cost-effective production, and higher reliability, self-aligned trench etching and hydrogen annealing techniques are developed. While maintaining low threshold voltage and simultaneously improving gate oxide integrity, the double-layer gate oxide technology was adapted. The trench gate power MOSFET was designed with a 0.6 μm trench width and 3.0 μm cell pitch. The evaluated on-resistance and breakdown voltage of the device were less than 24 mΩ and 105 V, respectively. The measured sensing ratio was approximately 70:1. Sensing ratio variations depending on the gate applied voltage of 4 V ~ 10 V were less than 5.6%.