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LED Matrix 헤드램프용 DPWM 기반 Analog Bypass Circuit in 180-nm CMOS
채종혁(Jong-Hyuk Chae),정재훈(Jae-Hun Jeong),박병하(Byeong-Ha Park),범진욱(Jin-Wook Burm) 대한전자공학회 2023 대한전자공학회 학술대회 Vol.2023 No.6
This paper presents a LED driver circuit that can bypass 1A current using 8-bit digital pulse width modulation(DPWM) in 180-nm CMOS technology. The operation of proposed circuit is divided into two parts. First, LED bypass circuit which bypasses 1A current with a supply voltage of 70V. Another part is total system which is combined with 8-bit counter based DPWM with a supply voltage of 5V. The proposed circuit controls luminosity of 8 LEDs by 256 steps. The circuit is simulated using Cadence Spectre. The simulation results and postsimulation results are presented in this paper.
무연 솔더가 적용된 자동차 전장부품 접합부의 열적.기계적 신뢰성 평가
하상수,김종웅,채종혁,문원철,홍태환,유충식,문정훈,정승부,Ha, Sang-Su,Kim, Jong-Woong,Chae, Jong-Hyuck,Moon, Won-Chul,Hong, Tae-Hwan,Yoo, Choong-Sik,Moon, Jeong-Hoon,Jung, Seung-Boo 대한용접접합학회 2006 대한용접·접합학회지 Vol.24 No.6
This study was focused on the evaluation of the thermo-mechanical board-level reliability of Pb-bearing and Pb-free surface mount assemblies. The composition of Pb-bearing solder was a typical Sn-37Pb and that of Pb-free solder used in this study was a representative Sn-3.0Ag-0.5Cu in mass %. Thermal shock test was chosen for the reliability evaluation of the solder joints. Typical $Cu_6Sn_5$ intermetallic compound (IMC) layer was formed between both solders and Cu lead frame at the as-reflowed state, while a layer of $Cu_3Sn$ was additionally formed between the $Cu_6Sn_5$ and Cu lead frame during the thermal shock testing. Thickness of the IMC layers increased with increasing thermal shock cycles, and this is very similar result with that of isothermal aging study of solder joints. Shear test of the multi layer ceramic capacitor(MLCC) joints was also performed to investigate the degradation of mechanical bonding strength of solder joints during the thermal shock testing. Failure mode of the joints after shear testing revealed that the degradation was mainly due to the excessive growth of the IMC layers during the thermal shock testing.
SPAD 항복 전압 Variation으로 인한 오차를 완화하기 위한 Quenching 회로 설계 및 최적화
정재훈(Jae-Hun Jeong),채종혁(Jong-Hyuk Chae),이승주(Seung-Ju lee),김영(Young Kim),범진욱(Jin-Wook Burm) 대한전자공학회 2023 대한전자공학회 학술대회 Vol.2023 No.6
Single-photon avalanche diode(SPAD) with Quenching Circuits are presented in this work. To reduce the variation according to SPAD characteristics, a current mirror was used as the passive quenching element. SPAD is designed as a deep n-well type. It was designed with a 110nm CMOS process, and the breakdown voltage difference due to process variation was directly measured.