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조군식(Cho Koon Shik),이순흠(Lee Sun Heum),임해진(Lim Hae Jin),김선형(Kim Sun Hyoung) 한국정보처리학회 1997 정보처리학회논문지 Vol.4 No.2
This paper presents the fundamental study to implement the wireless data link system in the subway. The propagation characteristics of the electromagnetic wave in the tunnel are analyzed to determine the proper radio frequencies for our system. The tunnel is modeled as a circular waveguide and then, its path loss is obtained. The efficient communication control procedure is proposed, which is well suited to our system architecture and the subway environment. The prototype system shows a good performance in the data communication.
DVB-T baseband 수신기를 위한 DSP 기반 SoC 플랫폼 설계
강승현 ( Seoung-hyun Kang ),조군식 ( Koon-shik Cho ),서우현 ( Woo-hyun Seo ),조준동 ( Jun-dong Cho ) 한국정보처리학회 2005 한국정보처리학회 학술대회논문집 Vol.12 No.1
본 논문에서는 기존의 설계 방법의 문제점을 해결하기 위한 설계 방법인 플랫폼 기반 설계에서 사용할 수 있는 DSP 기반 플랫폼을 구현하였다. 구현된 DSP 기반 플랫폼을 AMBA AHB 버스를 바탕으로 한 듀얼프로세서 플랫폼과 crossbar switch 구조의 버스 구조를 가지고 4개의 프로세서를 연결한 멀티프로세서 플랫폼으로 확장하여 검증함으로서 이질적인 환경에서 동작함을 나타내었다. 멀티프로세서 플랫폼에서는 DVB-T baseband 수신기를 HW/SW 분할 구현하고 성능 평가를 수행하였다. DSP 기반 플랫폼은 유연성, 확장성, 고속의 연산의 특징을 가진다.
개선된 ARM 7 코어와 peripheral 내장 프로세서 설계
조현우(Hyun-Woo Cho),허경철(Kyung-Chol Huh),송승원(Seung-Won Song),조군식(Koon-Shik Cho),최원태(Won-Tae Choi),김태훈(Tae-Hoon Kim),박주성(Ju-Sung Park) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.7
This paper deals with design of RISC processor, which is compatible with ARM7 and has some improvement. We designed a pipeline for the processor based on a p flip-flop, which solved the problem with the latch-based pipeline. Also, by modifying the structure of multiplier of the ARM7 core, we attempted to improve the performance of core. Additionally, the design includes AMBA BUS, audio codec interface, MMU, and built-in RAM of 192kbyte. The designed processor is fabricated with 0.18㎛ CMOS process. It is confirmed that the chip is compatible with the ARM7 through unit instruction test, combinational test of instructions, and running applications. It is also confirmed that the designed 32bit RISC processor has less calculation cycles in all applications than ARM7.
MPEG-2 AAC 디코더를 위한 고속 IMDCT 알고리즘
지화준(Hua-Jun Chi),김태훈(Tae-Hoon Kim),조군식(Koon-shik Cho),박주성(Ju-Sung Park) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.7
This paper proposes a new IFFT(Inverse Fast Fourier Transform) algorithm, which is proper for IMDCT((Inverse Modified Discrete Cosine Transform) of MPEG-2 AAC(Advanced Audio Coding) decoder. The IFFT used in 2<SUP>N</SUP>-point IMDCT employ the bit-reverse data arrangement of inputs and N/4-IFFT to reduce the calculation cycles. We devised a new data arrangement algorithm of IFFT input and N/4<SUP>n+1</SUP>-IFFT and can reduce multiplication cycles, addition cycles, and ROM size.
디지털 오디오 신호처리에 적합한 DSP 설계 및 FPGA 검증
류창원(Chang-Won Ryu),이동훈(Dong-Hun Lee),지화준(Hua-Jun Chi),김태훈(Tae-Hoon Kim),조군식(Koon-Shik Cho),박주성(Ju-Sung Park) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.7
This paper describes the design and verification process of a DSP, which is optimized for audio signal processing. We have run 5 audio algorithms on sixteen bit fixed point DSP, TMS320C542, to investigate the usage of each instruction, then choose the instruction sets that are used in implementing those algorithms. We can get ride of more than 100 instructions from TMS320C542's instructions based on that analysis. We have analyzed 3 conventional DSP to get idea for architecture design of target DSP. The DSP has data size of 24 bits to support high quality audio, and has 124 instructions and the complexity of 87,350 gates. The designed DSP was implemented in FPGA to accurately check the function with various test vectors. The test vectors consists of single instruction test, combination test of instructions, and audio applications.