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AAC 디코더의 IMDCT를 위한 고속 IFFT 알고리즘
지화준,김태훈,박주성,Chi, Hua-Jun,Kim, Tae-Hoon,Park, Ju-Sung 한국음향학회 2007 韓國音響學會誌 Vol.26 No.5
본 논문은 MPEG-2 AAC(Advanced Audio Boding) 디코더에 필요한 IMDCT(Inverse Modified Discrete Cosine Transform)를 고속으로 처리하기 위한 새로운 IFFT(Inverse Fast Fourier Transform) 구현 방식을 제안한다. 기존 방식 중에서 $2^n$(N-point) type IMDCT가 성능이 가장 우수하지만 많은 계산을 요구하는 N/4-point complex IFFT 과정을 포함하고 있다. 본 연구는 $2^n$(N-point) type IMDCT에 포함된 N/4-point complex IFFT의 연산량을 줄이는 방법을 고안하였다. N/4-point complex IFFT는 입력 데이터를 bit-reverse 방식을 사용하여 정렬하지만 본 연구에서는 새로운 입력 데이터 정렬방식과 $N/4^{n+1}$ 형태의 IFFT 고안하여 곱셈, 덧셈, ROM 용량을 줄였다. This paper proposes a new IFFT(Inverse Fast Fourier Transform) algorithm, which is proper for IMDCT(Inverse Modified Discrete Cosine Transform) of MPEG-2 AAC(Advanced Audio Coding) decoder. The $2^n$(N-point) type IMDCT is the most powerful among many IMDCT algorithms, however it includes IFFT that requires many calculation cycles. The IFFT used in $2^n$(N-point) type IMDCT employ the bit-reverse data arrangement of inputs and N/4-point complex IFFT to reduce the calculation cycles. We devised a new data arrangement method of IFFT input and $N/4^{n+1}$-type IFFT and thus we can reduce multiplication cycles, addition cycles, and ROM size.
MPEG-2 AAC 디코더를 위한 고속 IMDCT 알고리즘
지화준(Hua-Jun Chi),김태훈(Tae-Hoon Kim),조군식(Koon-shik Cho),박주성(Ju-Sung Park) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.7
This paper proposes a new IFFT(Inverse Fast Fourier Transform) algorithm, which is proper for IMDCT((Inverse Modified Discrete Cosine Transform) of MPEG-2 AAC(Advanced Audio Coding) decoder. The IFFT used in 2<SUP>N</SUP>-point IMDCT employ the bit-reverse data arrangement of inputs and N/4-IFFT to reduce the calculation cycles. We devised a new data arrangement algorithm of IFFT input and N/4<SUP>n+1</SUP>-IFFT and can reduce multiplication cycles, addition cycles, and ROM size.
디지털 오디오 신호처리에 적합한 DSP 설계 및 FPGA 검증
류창원(Chang-Won Ryu),이동훈(Dong-Hun Lee),지화준(Hua-Jun Chi),김태훈(Tae-Hoon Kim),조군식(Koon-Shik Cho),박주성(Ju-Sung Park) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.7
This paper describes the design and verification process of a DSP, which is optimized for audio signal processing. We have run 5 audio algorithms on sixteen bit fixed point DSP, TMS320C542, to investigate the usage of each instruction, then choose the instruction sets that are used in implementing those algorithms. We can get ride of more than 100 instructions from TMS320C542's instructions based on that analysis. We have analyzed 3 conventional DSP to get idea for architecture design of target DSP. The DSP has data size of 24 bits to support high quality audio, and has 124 instructions and the complexity of 87,350 gates. The designed DSP was implemented in FPGA to accurately check the function with various test vectors. The test vectors consists of single instruction test, combination test of instructions, and audio applications.