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A 150-Mb/s CMOS Monolithic Optical Receiver for Plastic Optical Fiber Link
박강엽,오원석,함경선,최우영 한국광학회 2012 Current Optics and Photonics Vol.16 No.1
This paper describes a 150-Mb/s monolithic optical receiver for plastic optical fiber link using a standard CMOS technology. The receiver integrates a photodiode using an N-well/P-substrate junction, a pre amplifier, a post amplifier, and an output driver. The size, PN-junction type, and the number of metal fingers of the photodiode are optimized to meet the link requirements. The N-well/P-substrate photodiode has a 200-μm by 200-μm optical window, 0.1-A/W responsivity, 7.6-pF junction capacitance and 113-MHz bandwidth. The monolithic receiver can successfully convert 150-Mb/s optical signal into digital data through up to 30-m plastic optical fiber link with -10.4 dBm of optical sensitivity. The receiver occupies 0.56-mm2area including electrostatic discharge protection diodes and bonding pads. To reduce unnecessary power consumption when the light is not over threshold or not modulating, a simple light detector and a signal detector are introduced. In active mode, the receiver core consumes 5.8-mA DC currents at 150-Mb/s data rate from a single 3.3 V supply, while consumes only 120 μW in the sleep mode.
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A Power-adjustable Fully-integrated CMOS Optical Receiver for Multi-rate Applications
박강엽,윤은정,오원석 한국광학회 2016 Current Optics and Photonics Vol.20 No.5
A power-adjustable fully-integrated CMOS optical receiver with multi-rate clock-and-data recoverycircuit is presented in standard 65-nm CMOS technology. With supply voltage scaling, key features ofthe optical receiver such as bandwidth, power efficiency, and optical sensitivity can be automaticallyoptimized according to the bit rates. The prototype receiver has -23.7 dBm to -15.4 dBm of opticalsensitivity for 10-9bit error rate with constant conversion gain around all target bit rates from 1.62Gbpsto 8.1 Gbps. Power efficiency is less than 9.3 pJ/bit over all operating ranges.
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Design and Implementation of a Photo Detector Using a Complementary Metal-Oxide Semiconductor
오원석,박강엽 한국물리학회 2010 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.57 No.61
In this paper, we present a photo detector using a complementary metal-oxide semiconductor (CMOS) for plastic optical fiber (POF) applications. Generally, the PIN photodiode and optical receiver front-end circuit are made from III-V compound materials, such as GaAs, InP, and HEMT (High Electron Mobility Transistor), due to their high speed and low noise characteristics. However, silicon deep-submicron CMOS technology is more attractive due to its low cost and high integration capacity. A PIN photodiode using a CMOS suffers from a low responsivity (R) a slow spreading speed of drift and diffusion current generated by photon. To overcome the low responsivity of the CMOS PIN photodiode, we exploit a PN junction between the N-well and the P-substrate. We propose a finger-shaped arrangement of the P-substrate to compensate for the slow spreading speed of the drift currents. The implemented CMOS PIN photodiode exhibits 0.12-A/W responsivity and 4.5-pF parasitic capacitance. Also, the optical receiver front-end circuit for the POF applications is integrated with the CMOS PIN photodiode. The designed photo detector exhibits a 112-MHz 3-dB bandwidth and consumes only 3-mA of DC current from a single 3.3 V supply voltage.
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A 12.5-Gb/s Optical Transmitter Using an Auto-power and -modulation Control
오원석,박강엽,임영민,김회경 한국광학회 2009 Current Optics and Photonics Vol.13 No.4
In this paper, a 12.5-Gb/s optical transmitter is implemented using 0.13-μm CMOS technology. The optical transmitter that we constructed compensates temperature effects of VCSEL (Vertical cavity surface emitting laser) using auto-power control (APC) and auto-modulation control (AMC). An external monitoring photodiode (MPD) detects optical power and modulation. The proposed APC and AMC demonstrate 5~20-mA of bias-current control and 5~20-mA of modulation-current control, respectively. To enhance the bandwidth of the optical transmitter, an active feedback amplifier with negative capacitance compensation is exploited. The whole chip consumes only 140.4-mW of DC power at a single 1.8-V supply under the maximum modulation and bias currents, and occupies the area of 1280-μm by 330-μm excluding bonding pads.
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ZigBee 응용을 위한 900MHz CMOS RF 송·수신기 구현
권재관,최우영,박강엽,오원석 대한전자공학회 2006 電子工學會論文誌-TC (Telecommunications) Vol.43 No.11
In this paper, we describe a 900MHz CMOS RF transceiver using an ISM band for ZigBee applications. The architecture of the designed rx front-end, which consists of a low noise amplifier, a down-mixer, a programmable gain amplifier and a band pass filter. And the tx front-end, which consists of a band pass filter, a programmable gain amplifier, an up-mixer and a drive amplifier. A low-if topology is adapted for transceiver architecture, and the total current consumption is reduced by using a low power topology. Entire transceiver is verified by means of post-layout simulation and is implemented in 0.18um RF CMOS technology. The fabricated chip demonstrate the measured results of -92dBm minimum rx input level and 0dBm maximum tx output level. Entire power consumption is 32mW(@1.8VDD). Die area is 2.3mm× 2.5mm including ESD protection diode pads. 본 논문은 ZigBee 응용을 위한 900MHz ISM 밴드용 RF 송수신기 설계에 관한 기술이다. 수신단은 저잡음 증폭기, 하향 믹서, 프로그래머블 이득증폭기, 밴드패스필터로 구성되며, 송신단은 밴드패스필터, 프로그래머블 이득증폭기, 상향믹서, 구동증폭기로 구성된다. 송수신단은 Low-IF 구조를 사용하였다. 또한, 송수신단을 구성하는 각각의 블록은 저전력 기술을 사용하여 전체적인 전류 소모를 줄였다. Post-레이아웃 시뮬레이션으로 전체 송수신기의 성능을 검증 하였으며, 0.18um RF CMOS 공정을 이용하여 칩으로 구현하였다. 측정결과 제작된 칩셋은 -92dBm의 최소 수신 입력 레벨을 갖으며, 0dBm의 선형적인 최대 송신 출력 레벨을 갖는다. 또한, 전력 소모는 32mW(@1.8VDD)이며, ESD 방지 다이오드 패드를 포함한 칩 면적은 2.3mm x 2.5mm이다.
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25-Gbps Depletion-Type 실리콘 링 변조기 성능 극대화를 위한 소자 구조 최적화
성민혁,조영관,김민규,박강엽,오원석,최우영 대한전자공학회 2021 전자공학회논문지 Vol.58 No.1
This paper proposes the performance optimization methodology of 25-Gbps depletion-type silicon-ring modulators, and experimentally verifies its effectiveness. A model is proposed that can describe the dependence of the dynamic modulation characteristics on the depletion-type silicon-ring modulator device structure. The model parameters that influence the ring modulator performance are identified, and their dependence on the device structure is investigated. With this, the optimal device structure that results in the best 25-Gbps eye diagrams is determined. The experimental results confirm the accuracy of our design optimization method. 본 논문은 실리콘 포토닉스 기반 depletion-type 링 변조기의 성능 최적화를 위한 소자 설계 방법을 제시하고, 이의 유효성을 실험적으로 검증한다. Depletion-type 실리콘 링 변조기의 소자 구조에 따른 동적 변조 특성 변화를 파악할 수 있는 모델을 구축하고, 이를 바탕으로 변조기의 25-Gbps eye diagram을 시뮬레이션하여 최적의 eye 성능을 갖는 소자 구조를 도출하며, 이 결과를 실험 결과와 비교한다.
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광수신기를 위한 2.5Gbps CMOS Transimpedance 증폭기 설계
전지호(J. H. Jeon),이은영(E. Y. Lee),심상미(S. M. Sim),박강엽(K. Y. Park),전석희(S. H. Jeon),유종근(C. G Yu) 대한전기학회 2008 대한전기학회 학술대회 논문집 Vol.2008 No.10
요즘 데이터의 양이 많아지고 마이크로프로세서의 속도가 빨라짐에 따라 광통신이 각광받고 있다. 광통신이란 전류신호를 광 신호로 변환하여 송신하고 광섬유를 통해 전달된 광신호가 포토다이오드를 통해 전류신호로 변환되어 수신하는 통신방법이다. TIA는 이런 광통신의 수신부의 첫 단에 오는 블록으로서 전류신호를 사용가능한 전압신호로 바꾸어주는 역할을 한다. 본 논문에서는 포토다이오드의 커패시턴스 성분을 효과적으로 차단하고 노이즈 특성을 향상시킬 수 있는 방법을 제안하고, 1.8V 0.18um CMOS공정을 사용하여 2.5Gbps TIA 블록을 설계하였다.
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