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HfO₂ MIM capacitor의 하부 금속에 따른 전기적 특성 변화
도승우(Seung-Woo Do),배군호(Kun-Ho Bae),이재성(Jae-Sung Lee),이용현(Yong-Hyun Lee) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.7
In this study, on the various metal electrodes a high-k dielectrics, HfO₂, thin film was deposited by reactive RF-magnetron sputtering method for the application of Metal-Insulator-Metal (MIM) capacitors. The metals, such as RuO₂, Pt, W, TiN and poly-Si were used as a bottom electrodes and AI as a top electrode. The characteristics of capacitance and leakage current depend on the interface properties between HfO₂ and the bottom electrode. Among the metals, Pt and W were g∞d candidates for a bottom electrode in the metal-HfO₂-metal structure.
HfO<sub>2</sub>/Hf/Si MOS 구조에서 나타나는 HfO<sub>2</sub> 박막의 물성 및 전기적 특성
배군호,도승우,이재성,이용현,Bae, Kun-Ho,Do, Seung-Woo,Lee, Jae-Sung,Lee, Yong-Hyun 한국전기전자재료학회 2009 전기전자재료학회논문지 Vol.22 No.2
In this paper, Thin films of $HfO_2$/Hf were deposited on p-type wafer by Atomic Layer Deposition (ALD). We studied the electrical and material characteristics of $HfO_2$/Hf/Si MOS capacitor depending on thickness of Hf metal layer. $HfO_2$ films were deposited using TEMAH and $O_3$ at $350^{\circ}C$. Samples were then annealed using furnace heating to $500^{\circ}C$. Round-type MOS capacitors have been fabricated on Si substrates with $2000\;{\AA}$-thick Pt top electrodes. The composition rate of the dielectric material was analyzed using TEM (Transmission Electron Microscopy), XRD (X-ray Diffraction) and XPS (X-ray Photoelectron Spectroscopy). Also the capacitance-voltage (C-V), conductance-voltage (G-V), and current-voltage (I-V) characteristics were measured. We calculated the density of oxide trap charges and interface trap charges in our MOS device. At the interface between $HfO_2$ and Si, both Hf-Si and Hf-Si-O bonds were observed, instead of Si-O bond. The sandwiched Hf metal layer suppressed the growing of $SiO_x$ layer so that $HfSi_xO_y$ layer was achieved. And finally, the generation of both oxide trap charge and interface trap charge in $HfO_2$ film was reduced effectively by using Hf metal layer.
ALD 방법으로 증착된 HfO2/Hf 박막을게이트 절연막으로 사용한 MOS 커패시터 제조
이대갑,도승우,이재성,이용현 대한전자공학회 2007 電子工學會論文誌-SD (Semiconductor and devices) Vol.44 No.5
In this paper, HfO2/Hf stacked film has been applied as the gate dielectric in MOS devices. The HfO2 thin film was deposited on p-type (100) silicon wafers by atomic layer deposition (ALD) using TEMAHf and O3 as precursors. Prior to the deposition of the HfO2 film, a thin Hf metal layer was deposited as an intermediate layer. Round-type MOS capacitors have been fabricated on Si substrates with 2000Å-thick Al or Pt top electrode. The prepared film showed the stoichiometric components. At the HfO2/Si interface, both Hf-Si and Hf-Si-O bonds were observed, instead of Si-O bond. The sandwiched Hf metal layer suppressed the growing of SiOx layer so that HfSixOy layer was achieved. It seems that the intermediate Hf metal layer has a benefit for the enhancement of electric characteristics of gate dielectric in HfO2/Si structure. 본 논문에서는 MOS 소자의 게이트 유전체로 사용될 고유전 박막으로 HfO2/Hf 박막을 제조하여 그 전기적 특성을 관찰하였다. HfO2 박막은 TEMAH와 O3 전구체를 사용한 ALD 방법으로 p-type (100) 실리콘 웨이퍼 위에 증착하였다. HfO2 막을 증착시키기 전에 중간층으로써 Hf 금속 층을 증착하였다. Round-type의 MOS 커패시터 제작을 위해, 상부 전극은 Al 또는 Pt을 이용하여 약 2000 Å 두께의 전극을 형성하였다. HfO2 박막은 화학정량적 특성을 보였으며, HfO2/Si 계면에서 Si-O 결합 대신 Hf-Si 결합과 Hf-Si-O 결합이 관찰되었다. HfO2와 Si 사이의 Hf 중간층은 SiOx의 성장이 억제되었고, HfSixOy으로 변형되었다. 이러한 결과로 HfO2/Hf/Si 구조에서 Hf 중간층이 있음으로 게이트 유전체의 고유전율이 유지되면서 계면 특성이 개선됨을 확인하였다.
중수소 이온 주입에 의한 MOS 커패시터의 게이트 산화막 절연 특성 개선
서영호,도승우,이용현,이재성,Seo, Young-Ho,Do, Seung-Woo,Lee, Yong-Hyun,Lee, Jae-Sung 한국전기전자재료학회 2011 전기전자재료학회논문지 Vol.24 No.8
This paper is studied for the improvement of the characteristics of gate oxide with 3-nm-thick gate oxide by deuterium ion implantation methode. Deuterium ions were implanted to account for the topography of the overlaying layers and placing the D peak at the top of gate oxide. A short anneal at forming gas to nitrogen was performed to remove the damage of D-implantation. We simulated the deuterium ion implantation to find the optimum condition by SRIM (stopping and range of ions in matter) tool. We got the optimum condition by the results of simulation. We compare the electrical characteristics of the optimum condition with others terms. We also analyzed the electrical characteristics to change the annealing conditions after deuterium ion implantation. The results of the analysis, the breakdown time of the gate oxide was prolonged in the optimum condition. And a variety of annealing, we realized the dielectric property that annealing is good at longer time. However, the high temperature is bad because of thermal stress.
마이크로 구조가 있는 소수성 표면에서 액적의 젖음성 상태에 대한 열역학적 모델 개발
유동인(Dong In Yu),도승우(Seoung Woo Doh),곽호재(Ho Jae Kwak),박현선(Hyun Sun Park),김무환(Moo Hwan Kim) 대한기계학회 2015 대한기계학회 춘추학술대회 Vol.2015 No.11
In this study, the wetting state on the hydrophobic micro-textured surfaces is experimentally and theoretically investigated. For the quantifiable analysis, the hydrophobic micro-textured surfaces are fabricated by MEMS (Micro Electro Mechanical Systems) technique. To clarify the wetting state depending on the geometrical morphology, the wetting state of a droplet on the surface is visualized by synchrotron X-ray radiography with a high spatial resolution (In this study, the size of a pixel was 1.74μm). On the basis of the visualized wetting state data, the thermodynamic model is theoretically developed to estimate the wetting state on the hydrophobic micro-textured surfaces.