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Woo Young Choi,Yong Jun Kim IEEE 2015 IEEE electron device letters Vol.36 No.9
<P>Complementary-metal-oxide-semiconductor (CMOS) and nanoelectromechanical (NEM) hybrid reconfigurable circuits are implemented for the first time using three-dimensional (3D) integration process. In addition, their operation is confirmed experimentally. For the fabrication of the 3D CMOS-NEM hybrid reconfigurable circuits, only the standard CMOS baseline process has been used except for the hydrofluoric acid vapor etch to release the NEM structures and focused-ion-beam patterning to define small patterns.</P>
CNTFET Based Ternary 1-Trit & 2-Trit Comparators for Low Power High-Performance Applications
Suman Rani,Balwinder Singh,Rekha Devi 한국전기전자재료학회 2021 Transactions on Electrical and Electronic Material Vol.22 No.6
1-Trit and 2-Trit Ternary comparator circuits using Complementary Metal–Oxide–Semiconductor (CMOS) as well as Carbon Nanotube Field-Effect Transistor (CNTFET) is proposed and investigated for Low Power High-performance applications. The design and simulation are investigated and authenticated using Hailey Simulation Program with Integrated Circuit (HSPICE) with Predictive technology model (PTM) low power 32 nm metal gate/High-K/Strained-Si Model for CMOS and 32 nm Stanford Model for CNTFET. The CNTFET based design is compared with the CMOS design in terms of signifi cant design aspects, specifically delay, Average Power consumption and Power delay product (PDP). A comparison is performed among CMOS and CNTFET based ternary comparator circuits which reveals that CNTFETs can lead to more efficient ternary circuits. In terms of delay and power consumption, the CNTFET based 1-Trit Ternary Comparator performs better than the CMOS based 1-Trit Ternary Comparator as the delay and Average power consumption are reduced by 89.7% and 57.3% in CNTFET type as compared to the CMOS based 1-Trit Ternary Comparator design. Similarly, in the case of the 2-Trit comparator, the CNTFET based design performs better than the CMOS-based design as the delay and Average power consumption are reduced by 88.7% and 42% in the CNTFET type.
A Complementary-Coupled CMOS <i>LC</i> Quadrature Oscillator
YUN, Seok-Ju,YOON, Dae-Young,LEE, Sang-Gug The Institute of Electronics, Information and Comm 2008 IEICE transactions on electronics Vol. No.
<P>A novel CMOS <I>LC</I> quadrature oscillator (QO) which adopts complementary-coupling circuitry has been proposed. The performance improvement in I/Q phase error and phase noise of the proposed QO, is explained in comparison with conventional QOs. The proposed QO is implemented in 0.18µm CMOS technology along with conventional QOs. The measurement result of the proposed QO shows -133.5dBc/Hz of phase noise at 1MHz offset and 0.6° I/Q phase difference, while oscillating at 1.77GHz. The proposed QO shows more than 6.5dB phase noise improvement compared to that of the conventional QOs over the offset frequency range of 10K-1MHz, while dissipating 4mA from 1.4V supply.</P>
Jau-Ji Jou,Tien-Tsorng Shih,Chih-Chen Peng,Hao-Wen Hsu,Xuan-Yi Ye 대한전자공학회 2021 Journal of semiconductor technology and science Vol.21 No.5
In this study, an inductorless broadband transimpedance amplifier (TIA) is implemented using TSMC 90-nm complementary metal-oxide-semiconductor (CMOS) technology. A regulated cascode circuit with low input impedance is used as the input stage of the TIA. The core amplifier is a fully differential amplifier with active feedback. The output stage of the TIA is an equalizer based on a differential amplifier with a source degenerated resistor and capacitor. The TIA has a bandwidth of 24.8 GHz and good linearity. In the TIA chip testing, clear 25-Gb/s nonreturn to zero and 50-Gb/s four-level pulse amplitude modulation eye diagrams can be observed.
새로 개발한 CMOS센서와 광원 및 필터를 이용한 증거 이미지의 질적인 향상
정진욱,권준철,박현도 한국과학수사학회 2020 과학수사학회지 Vol.14 No.3
범죄현장에서 증거를 찾는 감식의 가장 중요한 방법 중 하나는 빛의 특정 파장을 이용하여 지문 등잠재증거를 찾는 방법이다. 지금까지는 가시광선을 이용하여 현장에서 증거물을 감식하였으나 여러 종류의증거물과 미세한 증거에 적용하기에는 한계가 있었다. 그래서 다양한 빛의 파장에서도 증거물의 이미지를얻을 수 있는 촬영장비를 개발하였다. 일반적인 카메라의 센서는 가시광선만을 이미지화 하도록 설계되어있지만, 이번에 개발된 장비는 360~1,000 nm의 자외선부터 적외선까지 전체 빛의 파장 영역에서도 이미지를 얻을 수 있는 새로운 CMOS 센서를 탑재하였다. 또한 적외선 영역에서 650~1,000 nm까지는 장비의 내부에 장착한 정밀광학 필터가 광원의 파장 영역에 따라 각각 독립적으로 인식되면서 제어할 수 있기 때문에 이미지는 최대 4 K까지 선명도가 높아졌음을 확인할 수 있었다.
작은 Kvco 게인를 위한 직렬 바랙터와 병렬 캐패시터 뱅크를 이용한 CMOS 5GHz VCO 설계
이미영,Mi-Young Lee 한국인터넷방송통신학회 2024 한국인터넷방송통신학회 논문지 Vol.24 No.2
This paper presents the design of a voltage controlled oscillator (VCO) which is one of the key building blocks in modern wireless communication systems with small VCO gain (K<sub>vco</sub>) variation. To compensate conventional large K<sub>vco</sub> variation, a series varactor bank has been added to the conventional LC-tank with parallel capacitor bank array. And also, in order to achieve excellent phase noise performance while maintaining wide tuning range, a mixed coarse/fine tuning scheme(series varactor array and parallel capacitor array) is chosen. The switched varactor array bank is controlled by the same digital code for switched capacitor array without additional digital circuits. For use at a low voltage of 1.2V, the proposed current reference circuit in this paper used a current reference circuit for safety with the common gate removed more safely. Implemented in a TSMC 0.13㎛ CMOS RF technology, the proposed VCO can be tuned from 4.4GH to 5.3GHz with the K<sub>vco</sub> (VCO gain ) variation of less than 9.6%. While consuming 3.1mA from a 1.2V supply, the VCO has -120dBc/Hz phase noise at 1MHz offset from the carrier of the 5.3 GHz.
Post-Linearization of Differential CMOS Low Noise Amplifier Using Cross-Coupled FETs
Tae-Sung Kim,Seong-Kyun Kim,Jin-Sung Park,Byung-Sung Kim 대한전자공학회 2008 Journal of semiconductor technology and science Vol.8 No.4
A post-linearization technique for the differrential CMOS LNA is presented. The proposed method uses an additional cross-coupled common-source FET pair to cancel out the third-order intermodulation (IM₃) current of the main differential amplifier. This technique is applied to enhance the linearity of CMOS LNA using 0.18-㎛ technology. The LNA achieved +10.2 ㏈m IIP3 with 13.7 ㏈ gain and 1.68 ㏈ NF at 2 ㎓ consuming 11.8 ㎃ from a 1.8-V supply. It shows IIP3 improvement by 6.6 ㏈ over the conventional cascode LNA without the linearizing circuit.
Post-Linearization of Differential CMOS Low Noise Amplifier Using Cross-Coupled FETs
Kim, Tae-Sung,Kim, Seong-Kyun,Park, Jin-Sung,Kim, Byung-Sung The Institute of Electronics and Information Engin 2008 Journal of semiconductor technology and science Vol.8 No.4
A post-linearization technique for the differrential CMOS LNA is presented. The proposed method uses an additional cross-coupled common-source FET pair to cancel out the third-order intermodulation ($IM_3$) current of the main differential amplifier. This technique is applied to enhance the linearity of CMOS LNA using $0.18-{\mu}m$ technology. The LNA achieved +10.2 dBm IIP3 with 13.7 dB gain and 1.68 dB NF at 2 GHz consuming 11.8 mA from a 1.8-V supply. It shows IIP3 improvement by 6.6 dB over the conventional cascode LNA without the linearizing circuit.
Post-Linearization of Differential CMOS Low Noise Amplifier Using Cross-Coupled FETs
김태성,김성균,박진성,김병성 대한전자공학회 2008 Journal of semiconductor technology and science Vol.8 No.4
A post-linearization technique for the differrential CMOS LNA is presented. The proposed method uses an additional cross-coupled common-source FET pair to cancel out the third-order intermodulation (IM₃) current of the main differential amplifier. This technique is applied to enhance the linearity of CMOS LNA using 0.18-㎛ technology. The LNA achieved +10.2 ㏈m IIP3 with 13.7 ㏈ gain and 1.68 ㏈ NF at 2 ㎓ consuming 11.8 ㎃ from a 1.8-V supply. It shows IIP3 improvement by 6.6 ㏈ over the conventional cascode LNA without the linearizing circuit.
High-Isolation SPDT RF Switch Using Inductive Switching and Leakage Signal Cancellation
Choon Sik Cho,Byeong Wan Ha 한국전자파학회JEES 2014 Journal of Electromagnetic Engineering and Science Vol.14 No.4
A switch is one of the most useful circuits for controlling the path of signal transmission. It can be added to digital circuits to create a kind of gate-level device and it can also save information into memory. In RF subsystems, a switch is used in a different way than its general role in digital circuits. The most important characteristic to consider when designing an RF switch is keeping the isolation as high as possible while also keeping insertion loss as low as possible. For high isolation, we propose leakage signal cancellation and inductive switching for designing a singlepole double-throw (SPDT) RF switch. By using the proposed method, an isolation level of more than 23 dB can be achieved. Furthermore, the heterojunction bipolar transistor (HBT) process is used in the RF switch design to keep the insertion loss low. It is demonstrated that the proposed RF switch has an insertion loss of less than 2 dB. The RF switch operates from 1 to 8 GHz based on the 0.18-㎛ SiGe HBT process, taking up an area of 0.3 mm².