Dual delay line을 갖는 SAW 가스 센서의 제조 및 그 발진 특성

金龍希,崔東漢 경북대학교 센서기술연구소 1995 센서技術學術大會論文集 Vol.6 No.1

The SAW dual delay line structure of the gas sensor was designed and fabricated on the LiTaO_(3) substrate. The lead phthalocyanine(PbPc) thin film was deposited on the sensing delay line. Characteristics of the SAW device were investigated and a SAW delay line oscillator was constructed. To perceive effective frequency change in response to gas concentration, the operating frequency of the reference delay line oscillator and the sensing delay line oscillator must be match. So the operating frequency of the reference delay line oscillator was changed from 83.00MHz to 77.13MHz and the operating frequency of the sensing delay line oscillator was changed from 80.12MHz to 72.75MHz.

X-band Microwave Photonic Filter Using Switch-based Fiber-Optic Delay Lines

Byung-Min Jung 한국광학회 2018 Current Optics and Photonics Vol.2 No.1

An X-band microwave photonic (MWP) filter using switch-based fiber-optic delay lines has been proposed and experimentally demonstrated. It is composed of two electro-optic modulators (EOMs) and 2 × 2 optical MEMS-switch-based fiber-optic delay lines. By changing time-delay difference and coefficients of each wavelength signal by using fiber-optic delay lines and an electro-optic modulator, respectively, a bandpass filter or a notch filter can be implemented. For an X-band MWP filter with four channel elements, fiber-optic delay lines with the unit time-delay of 50 ps have been experimentally realized and the frequency responses corresponding to the time-delays has been measured. The measured frequency response error at center frequency and the time-delay difference error were 180 MHz at 10 GHz and 3.2 ps, respectively, when the fiber-optic delay line has the time-delay difference of 50 ps.

시간 측정범위 향상을 위한 펄스 트레인 입력 방식의 field-programmable gate array 기반 시간-디지털 변환기

김도형(Do-hyung Kim),임한상(Han-sang Lim) 대한전자공학회 2015 전자공학회논문지 Vol.52 No.6

Field-programmable gate array (FPGA) 기반 시간-디지털 변환기 (time-to-digital converter: TDC)는 구조가 단순하고, 빠른 변환속도를 갖는 딜레이 라인 (delay-line) 방식을 주로 사용한다. 하지만 딜레이 라인 방식 TDC의 시간 측정범위를 늘리기 위해서는 딜레이 라인의 길이가 길어지므로 사용되는 소자가 많아지고, 비선형성으로 인한 오차가 증가하는 단점이 있다. 따라서 본 논문은 동일한 길이의 딜레이 라인에 펄스 트레인 (pulse-train)을 입력하여 시간 측정범위를 향상시키고, 리소스를 효율적으로 사용하는 방식을 제안한다. 펄스 트레인 입력 방식의 TDC는 긴 시간을 측정하기 위하여 시작신호의 입력과 동시에 4-천이 (transition) 펄스 트레인이 딜레이 라인에 입력된다. 그리고 동기회로 (synchronizer) 대신 천이 상태 검출부를 설계하여 중지신호 입력 시 사용된 천이를 판별하고, 준안정 상태 (meta-stable state)를 피하면서 딜레이 라인의 길이를 줄이는 구조를 갖는다. 제안한 TDC는 72개의 딜레이 셀 (delay cell)을 사용하였고, 파인부 (fine interpolator)의 성능 측정 결과, 시간측정범위는 5070 ㎰, 평균 분해능은 20.53 ㎰, 최대 비선형성은 1.46 LSB였으며, 시간 측정범위는 계단 (step) 파형을 입력신호로 사용하는 기존 방식 대비 약 343 % 향상되었다. A delay-line type time-to-digital converter (TDC) implemented in a field-programmable gate array (FPGA) is most widely owing due to its simple structure and high conversion rate. However, the delay-line type TDC suffers from nonlinearity error caused by the long delay-line because its time interval measurement range is determined by the length of the used delay line. In this study, a new TDC structure with a shorter delay line by taking a pulse train as an input is proposed for improved time accuracy and efficient use of resources. The proposed TDC utilizes a pulse-train with four transitions and a transition state detector that identifies the used transition among four transitions and prevents the meta-stable state without a synchronizer. With 72 delay cells, the measured resolution and maximum non-linearity were 20.53 ps, and 1.46 LSB, respectively, and the time interval measurement range was 5070 ps which was enhanced by approximately 343 % compared to the conventional delay-line type TDC.

OCT 시스템을 위한 이중 광경로 지연기와 PZT 광경로 지연기에서의 편광모드분산 및 열요동 보상

김영관,박성진,김용평 경희대학교 레이저공학연구소 2004 레이저공학 Vol.15 No.-

In this study, a duplex scanning optical delay line is implemented and characterized for optical coherence tomography. The reference and sample arms in Michelson interferometer are simultaneously scanned by use of two identical piezoelectric transducers (PZT). It is obtained that scanning range, thermal drift, repeatability, and axial scanning velocity of duplex optical scanning delay line are distinctly superior to those of single scanning optical delay line.

광간섭 단층촬영(OCT)용 PZT 광경로 지연기에서의 편광모드 분산 및 열요동 보상

김영관,박성진,김용평,Kim, Young-Kwan,Park, Sung-Jin,Kim, Yong-Pyung 한국광학회 2005 한국광학회지 Vol.16 No.6

광간섭 단층촬영(OCT)용으로 원통형 압전소자(PZT)와 단일모드 광섬유를 이용한 광경로 지연기를 제작하여 그 특성을 분석하였다. 광경로 지연기에서 발생하는 편광모드 분산은 편광조절기로 조절하였고, 열요동을 2중 광경로 지연기를 구성하여 최소화하였다. 이중 광경로 지연기는 단일 광경로 지연기에 비해 2배의 측정 깊이와 속도를 구현하여 $18.6\pm0.5{\mu}m$의 해상도. 측정 깊이 1.68 mm, 측정 녹도 360.4 mm/s를 각각 얻었다. We have fabricated and characterized optical delay lines for optical coherence tomography, which is composed of cylindrical PZT(piezoelectric transducer) and single mode optical fiber. The polarization mode dispersion from the optical delay lines was compensated by the polarization controllers. By applying the duplex optical delay line, we minimized the thermal drift due to optical delay lines and obtained the scan range of 2 times that of a single optical delay line. The OCT system showed resolution of $18.6\pm0.5{\mu}m$, scanning range of 1.68mm, and scanning speed of 360.4mm/s.

Reconfigurable Optical Delay Lines Based on Single Folded Waveguides

Linjie Zhou,Tong Ye,Jianping Chen 한국물리학회 2011 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.58 No.42

We propose a novel single folded waveguide-based reconfigurable optical delay line. Due to waveguide self-coupling, light travels back and forth along the waveguide, forming resonances. With two phase shifters embedded in the waveguide, resonance modes and coupling can be conveniently controlled. Under proper phases, the delay line can be reconfigured to perform various types of delays. In particular, when the resonance input and mutual coupling strengths are properly matched, the group delay dispersion can be significantly reduced, favoring an optical signal delay with low distortion. The group delay can be continuously tuned at low tuning power by changing the phases.

Delay Study by Parasitic Capacitance Caused by Inverter Layout

이성영 한국과학기술원 반도체설계교육센터 2020 IDEC Journal of Integrated Circuits and Systems Vol.6 No.2

The propagation time can be obtained by using the rising edge of the CLOCK signal reaching the receiver. To do this, it is necessary to synchronize the start time by synchronizing the impulse generator used in the transmitter and the DTC (Digital-to-Time Converter) part used in the receiver. In the receiver, the reference clock enters the delay line of the DTC. At this time, a template signal is generated by using a signal generated through each delay line. In addition, time information can be obtained by using the signal generated by the impulse generator of the receiver transmitted from the transmitter and whether the template signal is correlated with the correlator. Therefore, the DTC's delay line affects the resolution of time information. Therefore, in this paper, we explain the difference and solution of the delay between the simulation in Schematic and the post-layout in the delay line of DTC.

PVT Variation 보상을 위한 Dynamically Phase Error 추적 기능을 갖춘 저전력 All Digital Delay Locked Loop

박건호,이재진,오성진,이강윤 한국전자파학회 2020 한국전자파학회논문지 Vol.31 No.7

본 논문은 저전력 Replica based all digital delay locked loop(ADDLL)를 제안한다. ADDLL에서 Phase detector(PD)는 위상차이를 감지하고, Accumulator(ACC)는 input clock 대비 output clock이 lead되거나 delay되는 시간을 카운트하여 증가시키거나 감소시킨다. 또한 Analog DLL에서 Charge pump(CP), Loop filter (LF)와 Voltage controlled delay line(VCDL)대신Accumulator(ACC)와 Digitally controlled delay line(DCDL)으로 교체해 Loop filter의 누설 전류를 줄이고, 크기를 줄인다. 본 논문에서는 ADDLL은 Replica DCDL을 이용하여 DLL이 잠긴 이후 temperature나 supply voltage가 변함으로 인해 발생될 수 있는 위상 오차를 감지하는 기술을 설명한다. ACC는 Main DCDL 내부의 delay를 조정하고 350~900 MHz의Operation frequency를 제공한다. 제안하는 ADDLL은 180 nm CMOS 공정으로 설계되었고, 625 MHz에서 Supply voltage 1.8 V를 사용하여 12 mW의 전력소모를 가진다. 레이아웃의 총 크기는 250×300 μm이다.

Field Programmable Gate Array 기반 다중 클럭과 이중 상태 측정을 이용한 시간-디지털 변환기

정현철(Hyun-Chul Jung),임한상(Hansang Lim) 대한전자공학회 2014 전자공학회논문지 Vol.51 No.8

Field programmable gate array 기반 시간-디지털 변환기(Time to Digital Converter)로 가장 널리 사용되는 딜레이 라인(tapped delay line) 방식은 딜레이 라인의 길이가 길어지면 정확도가 떨어지는 단점이 있다. 이에 본 논문에서는 동일한 시간해상도를 가지면서 딜레이 라인의 길이를 줄일 수 있도록 4 위상 클럭을 사용하고 이중 상태 판별 제어부를 가지는 시간-디지털 변환기 구조를 제안한다. 4 위상 클럭 별로 딜레이 라인 구성 시 발생하는 라인 간 딜레이 오차를 줄이기 위해 입력신호와 가장 가까운 클럭과의 시간 차이만 하나의 딜레이 라인으로 측정하고 어떤 위상 클럭이 사용되었는지를 판별하는 구조를 가졌다. 또한 싱크로나이저 대신 이중 상태 측정 state machine을 이용하여 메타스태이블을 판별함으로써, 싱크로나이저로 인한 딜레이 라인의 증가를 억제하였다. 제안한 시간-디지털 변환기(TDC)의 성능 측정 결과 1 ms의 측정 시간 범위에 대해 평균 분해능 22 ps, 최대 표준편차 90 ps을 가지며 비선형성은 25 ps였다. In a delay line type of a time-to-digital converter implemented in Field Programmable Gate Array, the timing accuracy decreases for a longer carry chain. In this paper, we propose a structure that has a multi-phase clock and a state machine to check metastability; this would reduce the required length of the carry chain with the same time resolution. To reduce the errors caused by the time difference in the four delay lines associated with a four-phase clock, the proposed TDC generates a single input pulse from four phase clocks and uses a single delay line. Moreover, the state machine is designed to find the phase clock that is used to generate the single input pulse and determine the metastable state without a synchronizer. With the measurement range of 1 ms, the measured resolution was 22 ps, and the non-linearity was 25 ps.

A 100-kS/s 8.3-ENOB 1.7-<named-content content-type='math' xlink:type='simple'> <inline-formula> <tex-math notation='TeX'> <tex> $\mu\hbox{W}$ </tex> </tex-math> </inline-formula></named-content> Time-Domain Analog-to-Digital Converter

Younghoon Kim,Changsik Yoo IEEE 2014 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 2 E Vol.61 No.6

<P>A 100-kS/s time-domain analog-to-digital converter (TDADC) with successive approximation register architecture provides 8.3 effective bits. The time-domain comparator of the TDADC is realized with only one delay line consisting of a digitally controlled delay line and a voltage-controlled delay line. Therefore, the linearity degradation due to the mismatch between multiple delay lines can be avoided. The TDADC has been implemented in a 0.11-μm CMOS process with a 0.127-mm<SUP>2</SUP> active silicon area. The TDADC consumes 1.7 μW from a 0.6-V supply voltage.</P>