A Symmetrical Floating Impedance Scaling Circuit with Improved Low-frequency Characteristics

Fujihiko MATSUMOTO,Syuzo NISHIOKA,Shota MATSUO,Takeshi OHBUCHI 대한전자공학회 2017 IEIE Transactions on Smart Processing & Computing Vol.6 No.6

Impedance scaling techniques are known as methods to realize large capacitance with a small capacitor. Recently, a symmetrical floating impedance scaling (SFIS) circuit was proposed. However, the circuit has restrictions on operations at a lower frequency. In this paper, improvement techniques for low-frequency characteristics of the SFIS circuit are proposed. In order to enhance the terminal resistance, a negative impedance converter (NIC) block is employed in the SFIS circuit. In addition, cascode transistors are introduced to enhance the internal resistance associated with a capacitor in the SFIS circuit. The proposed techniques make the pole frequency lower. The proposed SFIS circuit is applied to a third-order Chebyshev filter via simulation. Cutoff frequency fc of the filter is set to 100 Hz, and the passband ripple of the filter is set to 0.5 dB. Simulation results show that the filter employing the proposed SFIS circuit is superior to a conventional one.

HDTV 응용을 위한 3V 10b 33MHz 저전력 CMOS A/D 변환기

이강진,이승훈,Lee, Kang-Jin,Lee, Seung-Hoon 한국전기전자학회 1998 전기전자학회논문지 Vol.2 No.2

본 논문에서는 HDTV 응용을 위한 10b 저전력 CMOS A/D 변환기 (analog-to-digital converter : ADC) 회로를 제안한다. 제안된 ADC의 전체 구조는 응용되는 시스템의 속도와 해상도 등의 사양을 고려하여 다단 파이프라인 구조가 적용되었다. 본 시스템이 갖는 회로적 특성은 다음과 같이 요약할 수 있다. 첫째, 전원전압의 변화에도 일정한 시스템 성능을 얻을 수 있는 바이어스 회로의 선택적 채널길이 조정기법을 제안한다. 둘째, 고속 2단 증폭기의 전력소모를 줄이기 위하여 증폭기가 사용되지 않는 동안 동작 전류 공급을 줄이는 전력소모 최적화 기법을 사용한다. 넷째, 다단 파이프라인 구조에서 최종단으로 갈수록 정확도 및 잡음 특성 등에서 여유를 얻을 수 있는 점을 고려한 캐패시터 스케일링 기법의 적용으로 면적 및 전력소모를 감소시킨다. 제안된 ADC는 0.8 um double-poly double-metal n-well CMOS 공정 변수를 사용하여 설계 및 제작되었고, 시제품 ADC의 성능 측정 결과는 Differential Nonlinearity (DNL) ${\pm}0.6LSB$, Integral Nonlinearity (INL) ${\pm}2.0LSB$ 수준이며, 전력소모는 3 V 및 40 MHz 동작시에는 119 mW, 5 V 및 50 MHz 동작시에는 320 mW로 측정되었다. This paper describes a l0b CMOS A/D converter (ADC) for HDTV applications. The proposed ADC adopts a typical multi-step pipelined architecture. The proposed circuit design techniques are as fo1lows: A selective channel-length adjustment technique for a bias circuit minimizes the mismatch of the bias current due to the short channel effect by supply voltage variations. A power reduction technique for a high-speed two-stage operational amplifier decreases the power consumption of amplifiers with wide bandwidths by turning on and off bias currents in the suggested sequence. A typical capacitor scaling technique optimizes the chip area and power dissipation of the ADC. The proposed ADC is designed and fabricated in s 0.8 um double-poly double-metal n-well CMOS technology. The measured differential and integral nonlinearities of the prototype ADC show less than ${\pm}0.6LSB\;and\;{\pm}2.0LSB$, respectively. The typical ADC power consumption is 119 mW at 3 V with a 40 MHz sampling rate, and 320 mW at 5 V with a 50 MHz sampling rate.

Surpassing Tradeoffs by Separation: Examples in Transmission Line Resonators, Phase-Locked Loops, and Analog-to-Digital Converters

Sun, Nan,Andress, William F.,Woo, Kyoung-Ho,Ham, Don-Hee The Institute of Electronics and Information Engin 2008 Journal of semiconductor technology and science Vol.8 No.3

We review three examples (an on-chip transmission line resonator [1], a phase-locked loop [2], and an analog-to-digital converter [3]) of design tradeoffs which can in fact be circumvented; the key in each case is that the parameters that seem to trade off with each other are actually separated in time or space. This paper is an attempt to present these designs in such a way that this common approach can hopefully be applied to other circuits. We note reader that this paper is not a new contribution, but a review in which we highlight the common theme from our published works [1-3]. We published a similar paper [4], which, however, used only two examples from [1] and [2]. With the newly added content from [3] in the list of our examples, the present paper offers an expanded scope.

Surpassing Tradeoffs by Separation: Examples in Transmission Line Resonators, Phase-Locked Loops, and Analog-to-Digital Converters

Nan Sun,William F. Andress,Kyoungho Woo,Donhee Ham 대한전자공학회 2008 Journal of semiconductor technology and science Vol.8 No.3

We review three examples (an on-chip transmission line resonator [1], a phase-locked loop [2], and an analog-to-digital converter [3]) of design tradeoffs which can in fact be circumvented; the key in each case is that the parameters that seem to trade off with each other are actually separated in time or space. This paper is an attempt to present these designs in such a way that this common approach can hopefully be applied to other circuits. We note reader that this paper is not a new contribution, but a review in which we highlight the common theme from our published works [1-3]. We published a similar paper [4], which, however, used only two examples from [1] and [2]. With the newly added content from [3] in the list of our examples, the present paper offers an expanded scope.

Time-Domain Analog Signal Processing Techniques

Kang, Jin-Gyu,Kim, Kyungmin,Yoo, Changsik The Institute of Semiconductor Engineers 2020 Journal of semiconductor engineering Vol.1 No.2

As CMOS technology scales down, the design of analog signal processing circuit becomes far more difficult because of steadily decreasing supply voltage and smaller intrinsic gain of transistors. With sub-1V supply voltage, the conventional analog signal processing relying on high-gain amplifiers is not an effective solution and different approach has to be sought. One of the promising approaches is "time-domain analog signal processing" which exploits the improving switching speed of transistors in a scaled CMOS technology. In this paper, various time-domain analog signal processing techniques are explained with some experimental results.

다중위상-그레이코드 카운터를 이용한 적외선 센서용 저전력 ADC 설계

김영선(Yeong Seon Kim),장병탁(Byung Tak Jang),임현자(Hyun Ja Im),이희철(Hee Chul Lee) 대한전자공학회 2018 전자공학회논문지 Vol.55 No.10

본 논문에서는 저전력 적외선 영상 시스템을 위하여, 다중위상-그레이코드 카운터를 적용한 아날로그 디지털 변환 회로(Analog to Digital Converter, ADC)를 제안하였다. 제안한 회로는 column-level single slope ADC 구조에 다중위상-그레이코드 카운터를 적용하여 기존의 이진수 디지털 카운터에서 요구하는 클럭 주파수를 낮추어 전력소모를 감소시키고, 디지털 노이즈에 강인한 특성을 갖는다. 또한 CTIA ramp 회로, column 별 비교기와 메모리를 통해 다중 column에서 입력되는 적외선 입력 신호를 동시에 변환할 수 있다. 제안한 회로는 0.18um CMOS 공정을 통해 설계 되었으며, 단위 column 회로의 전력소모는 171uW 이다. In this paper, we proposed an analog to digital converter(ADC) with multi phase-gray code digital counter for low power infrared image system. The proposed column-level single slope ADC can reduce clock frequency required in conventional binary digital counter and have lower power consumption with robustness to digital noise. Furthermore, the designed CTIA ramp generator, comparator and memory in each column can convert the multiple column infrared input signal at the same time. The proposed circuit was designed with 0.18um CMOS process. The power consumption result of the proposed unit column circuit was 171uW.

저-전압 연속-시간 아날로그 집적회로 필터의 설계에 관한 연구

崔仲鎬 서울시립대학교 산업기술연구소 1996 산업기술연구소논문집 Vol.4 No.-

The programmable continuous-time analog integrated filter is designed using a new biquad circuit block which can be properly applied to low-voltage applications. The new biquad circuit consists of wide-range controllable transconductance amplifiers (TA's) with reconfigurable multi-valued capacitor arrays. It uses two additional TA's to compensate the finite output resistance of a current-summing node without using the cascode technique for low supply voltage environments. The control voltage can be automatically generated together with ω0 and Q compensation blocks. Simulation results show significant performance improvement over the conventional approach. The filter was fabricated in a 0.8-μm CMOS technology and can be applied to various applications from audio to video signal processing.

Area-efficient Ramp Signal-based Column Driving Technique for AMOLED Panels

Tai-Ji An,Moon-Sang Hwang,Won-Jun Choe,Jun-Sang Park,Gil-Cho Ahn,Seung-Hoon Lee 대한전자공학회 2019 Journal of semiconductor technology and science Vol.19 No.4

This work proposes a ramp signal-based column driving technique to maximize the area efficiency of the column driver integrated circuit (IC) for high-resolution active-matrix organic light emitting diodes (AMOLED) panels. The proposed column driving technique replaces the 2<SUP>n</SUP> reference voltages coming from the conventional n-bit resistor digital-to-analog converters (RDAC) with a single ramp signal, thereby reducing the area of the column driver IC by 44.3%. A weighted two-step interpolation structure, composed of the first-stage 6-bit ramp signal and the second-stage 2-bit amplifier DAC, reduces the required operation speed of the ramp signal under a limited 1-horizontal (1-H) time, while processing 8-bit image signals. The performance of the proposed column driving technique is verified with a 96-channel prototype IC fabricated in a 0.18 μm CMOS process. The deviation of voltage output (DVO) of the prototype IC are within ±6 mV, and the unit channel area is 4200 μ㎡.

A 15-V Bidirectional Ultrasound Interface Analog Front-End IC for Medical Imaging Using Standard CMOS Technology

Banuaji, Aditya,Hyouk-Kyu Cha IEEE 2014 IEEE transactions on circuits and systems. a publi Vol.61 No.8

<P>A high-voltage (HV) interface analog front-end (AFE) integrated circuit (IC) for medical ultrasound imaging applications using 0.18-μm standard CMOS process is presented. The proposed AFE IC includes a HV pulser in the transmit path that safely generates up to 15-Vpp of unipolar pulses at 2.6 MHz, a HV switch for isolation between transmitter and receiver frontend parts, and a 95.1-dBΩ low-power transimpedance preamplifier with 12-MHz bandwidth and 3.5-pA/√Hz input referred noise in the receive path operating at a low 1.1-V supply voltage. Both the pulser and the switch utilize dynamically-gate-biased stacked 3.3-V transistors to enable HV operation without compromising device reliability. The implemented single-channel AFE IC prototype intended for interfacing capacitive micromachined ultrasound transducer consumes 0.15 mm2 of core die area, making it feasible to be applied for various multi-array medical ultrasound imaging systems.</P>

Design of Two-Stage Class AB CMOS Buffers: A Systematic Approach

Antonio Lopez Martin,Jose Maria Algueta Algueta,Lucia Acosta,Jaime Ramirez-Angulo,Ramon Gonzalez Carvajal 한국전자통신연구원 2011 ETRI Journal Vol.33 No.3

A systematic approach for the design of two-stage class AB CMOS unity-gain buffers is proposed. It is based on the inclusion of a class AB operation to class A Miller amplifier topologies in unity-gain negative feedback by a simple technique that does not modify quiescent currents, supply requirements, noise performance, or static power. Three design examples are fabricated in a 0.5 μm CMOS process. Measurement results show slew rate improvement factors of approximately 100 for the class AB buffers versus their class A counterparts for the same quiescent power consumption (< 200 μW).