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고집적 기억 소자를 위한 초박막 ONO 구조의 특성에 관한 연구
이성배,서광열 광운대학교 신기술연구소 1997 신기술연구소논문집 Vol.26 No.-
본 논문에서 저전압 비휘발성 반도체 기억소자(NVSM)를 위한 scaled ONO(oxide-nitride-oxide)구조의 박막조성과 특성을 조사하였다. 이를 위해 터널링 산화막 20Å질화막 46Å블로킹 산화막 40Å 초박막 ONO 구조의 커패시터형 scaled MONOS 기억소자를 제작하였다. 제작된 ONO 유전막의 조성과 결합 상태는 Auger 분석으로 조사하였으며, 이로부터 scaled ONO 구조에서 블로킹 산화막 성장시 상당량의 O가 질화막 내로 확산하여 질화막이 oxynitride와 같은 특성을 갖게됨을 알 수 있었다. C-V 방법을 이용하여 스위칭 특성을 조사한 결과 6V, 20msec. 의 프로그래밍 조건에서 소자를 소거 상태에서 기록 상태로 스위칭할 수 있었으며, scale-down에도 불구하고 △V_FB,max=4.56V의 최대 평탄밴드 전압 이동량을 얻었다. scaled ONO 구조에서 블로킹 산화막-질화막 계면 트랩의 기억특성에 대한 기여는 90% 이상이었다. 최적 일치 방법으로 구한 질화막 벌크트랩과 블로킹 산화막-질화막 계면 트랩의 밀도는 각각 N_T=7.4×10^l8cm^-3, N_ON=2.3×10^13cm^-2이었다. This paper examines the composition and characteristics of scaled ONO superthin film for future low voltage NVSM applications. Capacitor type MONOS devices with superthin film of 20Åunneling oxide, 46Åitride and 40Ålocking oxide were fabricated. The condition and composition of each layer in ONO dielectrics have been analyzed by Auger depth profile. It is shown in the scaled ONO structure that oxygen is diffused through the thin nitride and oxidized the nitride bulk to form an oxynitride-like layer. High frequency C-V method have been utilized to investigate the switching characteristics. The device can be switched from erased state to a written state by applying a programming voltage of 6V for a programming time of 20msec.In spite of scaling down, the maximum flatband voltage, △V_FB,max=4.56V has been obtained. The scaled nitride layer and nitride-blocking oxide interface permits the storage of charge resulting in adjustable threshold voltages. The contribution of a blocking oxide-nitride interface traps to the memory characteristics is over 90% in a scaled ONO structures. The concentration of nitride bulk traps, N_T=7.4×10^18cm^-3 and blocking oxide-nitride interface traps, N_ON=2.3 ×10^13cm^-2 were determined using the best fitting method.
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이흥규,이운영,임기조,김용주,Lee, Heung-Gyu,Lee, Un-Yeong,Im, Gi-Jo,Kim, Yong-Ju 대한전기학회 1999 전기학회논문지C Vol.48 No.8
Electrical conduction characteristics of XLPE film evaporated with different metal electrode are discussed. The relation between electrical current(I) and Voltage(V) in the M(metal)-I(XLPE)-M(metal) structure are measured in the temperature range from 25$[^{\circ}C]$ to 90[$[^{\circ}C]$ . Several kinds of metals are used as electrode, such as, Al, Ag and Cu.From the experimental results, it is conclused that the conduction mechanism at highelectric field is SCLC. The dependences of temperature and kinds of metal on the trap filled electric field level can be well explained by this theory.
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정양희,이영선,박영걸 한국전기전자재료학회 1994 電氣電子材料學會誌 Vol.7 No.3
The multi-dielectric layer $SiO_2$/$Si_3{N_4}$/$SiO_2$ (ONO) is used to improve charge retention and to scale down the memory device. The nitride layer of MNOS device is oxidize to form ONO system. During the oxidation of the nitride layer, the change of thickness of nitride layer and generation of interface state between nitride layer and top oxide layer occur. In this paper, effects of oxidation of the nitride layer is studied. The decreases of the nitride layer due to oxidation and trapping characteristics of interface state of multi layer dielectric film are investigated through the C-V measurement and F-N tunneling injection experiment using SONOS capacitor structure. Based on the experimental results, carrier trapping model for maximum flatband voltage shift of multi layer dielectric film is proposed and compared with experimental data. As a results of curve fitting, interface trap density between the top oxide and layer is determined as being $5{\times}10^11$~$2{\times}10^12$[$eV^1$$cm^2$].
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플래시메모리를 위한 Scaled SONOSFET NVSM의 프로그래밍 조건과 특성에 관한 연구
박희정,박승진,남동우,김병철,서광열 한국전기전자재료학회 2000 전기전자재료학회논문지 Vol.13 No.11
When the charge-trap type SONOS(polysilicon-oxide-nitride-oxide-semiconductor) cells are used to flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM(Nonvolatile Semiconductor Memory) cells were fabricated using 0.35 ㎛ standard memory cell embedded logic process including the ONO cell process, based on retrograde twin-well, single-poly, single metal CMOS(Complementary Metal Oxide Semiconductor) process. The thickness of ONO triple-dielectric for the memory cell is tunnel oxide of 24 $\AA$, nitride of 74 $\AA$, blocking oxide of 25 $\AA$, respectively. The program mode(V$\_$g/=7, 8, 9 V, V$\_$s/=V$\_$d/=-3 V, V$\_$b/=floating) and the erase mode(V$\_$g/=-4, -5, -6 V, V$\_$s/=V$\_$d/=floating, V$\_$b/=3 V) by MFN(Modified Fowler-Nordheim) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation(ΔV$\_$th/, S, G$\_$m/) characteristics than channel MFN tunneling operation. Also, the program inhibit conditins of unselected cell for separated source lines NOR-type flash memory application were investigated. we demonstrated that the phenomenon of the program disturb did not occur at source/drain voltage of 1 V∼12 V and gate voltage of -8 V∼4 V.
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