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A Design of the MB-OFDM UWB Frequency Synthesizer with a New Coarse Tuning Scheme
Young-Gun Pu,Dong-Hyun Ko,Joon-Sung Park,Chul Nam,Kang-Yoon Lee 대한전자공학회 2008 ICEIC:International Conference on Electronics, Inf Vol.1 No.1
This paper describes a 3 to 5㎓ frequency synthesizer for MB-OFDM (multi-band OFDM) UWB (Ultra-Wideband) application using 0.13㎛ CMOS process. The frequency synthesizer operates in the band group1 whose center frequencies are 3432㎒, 3960㎒, and 4488㎒. To cover the overall frequencies of group 1, an efficient frequency planning minimizing a number of blocks and the power consumption are proposed. And, a highfrequency VCO and prescaler architecture are also presented in this paper. A new coarse tuning scheme that utilizes the MIM capacitance and the varactor is proposed to expand the VCO tuning range. The single PLL and two SSB-mixers consume 75㎽ from a 1.5V supply. The VCO tuning range is 500㎒. The simulated phase noise of the VCO is -110㏈c/㎐ at 1㎒ offset. The die area is 3 × 2㎟.
A Design of CMOS Analog Front-End for PLC
Young Gun Pu,Jin Kyoung Kim,Ji Hoon Jung,Dong Hyun Ko,Kang-Yoon Lee 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
This paper presents a full-CMOS single-chip PHY IC for Power Line Communication (PLC) systems. To achieve the low power operation and the low cost, the analog front-end is designed with full-CMOS 0.25㎛ technology. In the Rx part, the Pre-Amp and Programmable Gain Amplifier (PGA) is designed to have a wide dynamic range and gain control range because the signal from the power line is variable depending on the distance. In the Tx part, the proposed Line Driver can drive the power line without external driving circuits composed of BJT and diode device. This chip is fabricated with 0.25㎛ CMOS technology, and the die area is 3.2㎜ × 3.2㎜. The power consumption is 25㎽ at 3.0V supply voltage in Rx mode, and 325㎽ at Tx mode, respectively.
PLC 시스템을 위한 CMOS Analog Front-End 설계
부영건(Young Gun Pu),김진경(Jin Kyoung Kim),정지훈(Ji Hoon Jung),고동현(Dong Hyun Ko),이강윤(Kang-Yoon Lee) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
This paper presents a Full-CMOS single-chip for Power Line Communication(PLC) systems. To achieve the low power operation and the low cost, the Analog Front-End is designed with Full-CMOS 0.25㎛ technology. In the Rx part, the Pre-Amp and Programmable Gain Amplifier (PGA) is designed to have a wide dynamic range and gain control range because the signal from the power line is variable depending on the distance. In the Tx part, the proposed Line Driver can drive the power line without external driving circuits composed of BJT and diode device. This chip is fabricated with 0.25㎛ CMOS technology, and the die area is 3.2㎜ × 3.2㎜. The power consumption is 25㎽ at 3.0V supply voltage in Rx mode, and 325㎽ at Tx mode, respectively.
넓은 출력 전압 범위를 갖는 위상동기루프를 위한 저전압 Charge Pump 회로 설계
부영건(Young Gun Pu),고동현(Dong Hyun Ko),김상우(Sang Woo Kim),박준성(Joon Sung Park),이강윤(Kang-Yoon Lee) 대한전자공학회 2008 電子工學會論文誌-SD (Semiconductor and devices) Vol.45 No.8
본 논문에서는 UWB PLL charge pump 의 충/방전 전류오차를 최소화하기 위한 회로를 제안하였다. Common-gate 와 Common-source 증폭기를 추가한 피드백 전압 조정기를 구성하여 높은 응답성을 가지는 charge pump를 설계하였다. 제안한 회로는 넓은 동작 영역을 갖으며, 낮은 전원 전압으로도 뛰어난 성능을 보인다. 본 회로는 1.2V 공급 전압과 IBM 0.13㎛ CMOS 공정으로 집적되었다. 설계의 효율성을 평가하기 위해 참고 논문의 다른 회로와 성능을 대조하였다. In this paper, a new circuit is proposed to minimize the charging and discharging current mismatch in charge pump for UWB PLL application. By adding a common-gate and a common-source amplifier and building the feedback voltage regulator, the high driving charge pump currents are accomplished. The proposed circuit has a wide operation voltage range, which ensures its good performance under the low power supply. The circuit has been implemented in an IBM 0.13㎛ CMOS technology with 1.2V power supply. To evaluate the design effectiveness, some comparisons have been conducted against other circuits in the literature.
Park, Young-Jun,Park, Hyung-Gu,Lee, Juri,Oh, Seong Jin,Jang, Jae Hyeong,Kim, Sang Yun,Pu, Young Gun,Hwang, Keum Cheol,Yang, Youngoo,Seo, Munkyo,Lee, Kang-Yoon Springer-Verlag 2016 Analog integrated circuits and signal processing Vol.86 No.2
<P>This paper presents a full-CMOS receiver for an A4WP application. Two schemes were used in the proposed synchronous rectifier to increase the efficiency of the rectifier. One scheme involves a limiting reverse current that senses the output load current by changing the half synchronous rectifier mode and full synchronous rectifier mode. Another scheme proposes a high efficiency active rectifier with a delay locked loop (DLL), which is a highly efficient receiver circuit intended for use in resonant wireless charging applications with a 6.78 MHz resonant frequency. Each metal-oxide-semiconductor field-effect transistor of the proposed rectifier uses an AC input voltage for the on/off operation. Concurrently, the DLL can compensate for the delay caused by the voltage limiter, level shifter, and gate driver, which leads to the removal of the reverse leakage current and maximizes the power efficiency. This chip is implemented using 0.18 mu m technology with an active area of around 2.3 mm x 1.5 mm. When the magnitude of the AC input voltage is 10 V, the maximum efficiency of the proposed rectifier is 94.2 %. The range of AC input voltages is 3-20 V.</P>
Park, Young-Jun,Park, Ju-Hyun,Kim, Hongjin,Pu, Young Gun,Hwang, Keum Cheol,Yang, Youngoo,Park, Cheon-Seok,Lee, Kang-Yoon Springer-Verlag 2016 Analog Integrated Circuits and Signal Processing Vol.88 No.1
<P>This paper presents a power managements IC for power transmitting unit (PTU) of magnetic resonant A4WP application. A high efficiency step-up converter with a programmable output is proposed to provide supply voltage to the external power amplifier with a peak power of 37.5 W. In order to implement the closed loop gain control function of the PTU with the power receiving unit, the duty cycle is controlled with the pulse width modulation signal from bluetooth low energy. The chip is fabricated using a 0.18 mu m BCD process with high power MOSFET options, and the die area is 4000 mu m x 4000 mu m. The measured maximum power efficiency of the step-up converter and step-down converter is each 92.8 % at load current of 0.5 A and 93.8 % at load current of 0.3 A. The output voltage of the step-up converter ranges from 12 to 25 V and that of the step-down converter ranges from 3.3 and 5 V.</P>
Donghyun Ko,Young-Gun Pu,Sangwoo Kim,Joon-Sung Park,Byung-Hak Cho,Kang-Yoon Lee 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
This paper presents a integrated Digitally Controlled Crystal Oscillator (DCXO) for PHS application. The frequency tuning is done by two-step MIM capacitor tuning scheme. The coarse tuning covers the frequency range of ±24ppm of the nominal frequency with the resolution of 0.75ppm. On the other hand, the fine tuning covers the frequency range of ±15ppm of the nominal frequency with the resolution of 0.12ppm. This chip is fabricated with 0.25㎛ CMOS technology, and the die area is 0.43㎜ × 0.55㎜ including PADs.
Full CMOS Single Supply PLC SoC ASIC with Integrated Analog Front-End
Nam, Chul,Pu, Young-Gun,Kim, Sang-Woo,Lee, Kang-Yoon The Institute of Electronics and Information Engin 2009 Journal of semiconductor technology and science Vol.9 No.2
This paper presents a single supply PLC SoC ASIC with a built-in analog Front-end circuit. To achieve the low power consumption along with low cost, this PLC SoC employs fully CMOS Analog Front End (AFE) and several LDO regulators (LDOs) to provide the internal power for Logic Core, DAC and Input/output Pad driver. The receiver part of the AFE consists of Pre-amplifier, Gain Amplifier and 1 bit Comparator. The transmitter part of the AFE consists of 10 bit Digital Analog Converter and Line Driver. This SoC is implemented with 0.18 ${\mu}m$ 1 Poly 5 Metal CMOS Process. The single supply voltage is 3.3 V and the internal powers are provided using LDOs. The total power consumption is below 30 mA at stand-by mode to meet the Eco-Design requirement. The die size is 3.2 $\times$ 2.8 $mm^{2}$.
Full CMOS Single Supply PLC SoC ASIC with Integrated Analog Front-End
Chul Nam,Young-Gun Pu,Sang-Woo Kim,Kang-Yoon Lee 대한전자공학회 2009 Journal of semiconductor technology and science Vol.9 No.2
This paper presents a single supply PLC SoC ASIC with a built-in analog Front-end circuit. To achieve the low power consumption along with low cost, this PLC SoC employs fully CMOS Analog Front End (AFE) and several LDO regulators (LDOs) to provide the internal power for Logic Core, DAC and Input/output Pad driver. The receiver part of the AFE consists of Pre-amplifier, Gain Amplifier and 1 bit Comparator. The transmitter part of the AFE consists of 10 bit Digital Analog Converter and Line Driver. This SoC is implemented with 0.18 ㎛ 1 Poly 5 Metal CMOS Process. The single supply voltage is 3.3 V and the internal powers are provided using LDOs. The total power consumption is below 30 ㎃ at stand-by mode to meet the Eco-Design requirement. The die size is 3.2 x 2.8 ㎟.
Hongjin Kim,Young-Jun Park,Ju-Hyun Park,Ho-Cheol Ryu,Young-Gun Pu,Minjae Lee,Keumcheol Hwang,Younggoo Yang,Kang-Yoon Lee 전력전자학회 2016 JOURNAL OF POWER ELECTRONICS Vol.16 No.6
This paper presents a DC-DC buck converter with a Phase-Locked Loop (PLL) that can compensates for power efficiency degradation over a wide input range. Its switching frequency is kept at 2 ㎒ and the delay difference between the High side driver and the Low side driver can be minimized with respect to Process, Voltage and Temperature (PVT) variations by adopting the PLL. The operation mode of the proposed DC-DC buck converter is automatically changed to Pulse Width Modulation (PWM) or PWM frequency modes according to the load condition (heavy load or light load) while supporting a maximum load current of up to 1.2 A. The PWM frequency mode is used to extend the CCM region under the light load condition for the PWM operation. As a result, high efficiency can be achieved under the light load condition by the PWM frequency mode and the delay compensation with the PLL. The proposed DC-DC buck converter is fabricated with a 0.18 ㎛ BCD process, and the die area is 3.96 ㎟. It is implemented to have over a 90 % efficiency at an output voltage of 5 V when the input range is between 8 V and 20 V. As a result, the variation in the power efficiency is less than 1 % and the maximum efficiency of the proposed DC-DC buck converter with the PLL is 95.4 %.