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Jo, Hongil,Song, Seung Yoon,Cho, Eunjeong,So, Jongho,Lee, Suheon,Choi, Kwang Yong,Ok, Kang Min American Chemical Society 2017 Inorganic chemistry Vol.56 No.15
<P>A novel lithium-rich transition metal selenite, Li13Mn(SeO3)(8), that is composed of a Jahn-Teller distortive cation., Mn3+, in the high spin d(4) state, and a second-order Jahn-Teller (SOJT) distortive lone pair cation, Se4+, has been synthesized via hydrothermal and high temperature solid state reactions. The selenite is classified as a molecular compound consisting of MnO6 octahedra, SeO3 trigonal pyramids, and Li+ cations. Considering the Li-O interactions, the structure of Li13Mn(SeO3)(8) may be described as a pseudo-three-dimensional framework as well. The title compound is thermally stable up to 500 degrees C and starts decomposing above the temperature attributable to the volatilization of SeO2. While the MnO6 octahedra in Li13Mn(SeO3)(8) exhibit six identical Mn-O bond distances at room temperature due to the dynamic Jahn-Teller effect, a clear elongation of two Mn-O bonds along a specific direction is observed at 100 K. A series of isostructural selenites with different transition metals, i.e., Li13M(SeO3)(8) (M = Sc, Cr, and Fe), have been also successfully obtained in phase pure forms using, similar synthetic methods. Magnetic properties, spectroscopic characterizations, and local dipole moments calculations for all the synthesized selenites ate presented.</P>
Sanguhn Cha,Hongil Yoon 대한전자공학회 2012 Journal of semiconductor technology and science Vol.12 No.4
In this paper, efficient implementation of error correction code (ECC) processing circuits based on single error correction and double error detection (SEC-DED) code with check bit pre-computation is proposed for memories. During the write operation of memory, check bit pre-computation eliminates the overall bits computation required to detect a double error, thereby reducing the complexity of the ECC processing circuits. In order to implement the ECC processing circuits using the check bit precomputation more efficiently, the proper SEC-DED codes are proposed. The H-matrix of the proposed SEC-DED code is the same as that of the odd-weightcolumn code during the write operation and is designed by replacing 0’s with 1’s at the last row of the H-matrix of the odd-weight-column code during the read operation. When compared with a conventional implementation utilizing the oddweight-column code, the implementation based on the proposed SEC-DED code with check bit precomputation achieves reductions in the number of gates, latency, and power consumption of the ECC processing circuits by up to 9.3%, 18.4%, and 14.1% for 64 data bits in a word.
Cha, Sanguhn,Yoon, Hongil The Institute of Electronics and Information Engin 2012 Journal of semiconductor technology and science Vol.12 No.4
In this paper, efficient implementation of error correction code (ECC) processing circuits based on single error correction and double error detection (SEC-DED) code with check bit pre-computation is proposed for memories. During the write operation of memory, check bit pre-computation eliminates the overall bits computation required to detect a double error, thereby reducing the complexity of the ECC processing circuits. In order to implement the ECC processing circuits using the check bit pre-computation more efficiently, the proper SEC-DED codes are proposed. The H-matrix of the proposed SEC-DED code is the same as that of the odd-weight-column code during the write operation and is designed by replacing 0's with 1's at the last row of the H-matrix of the odd-weight-column code during the read operation. When compared with a conventional implementation utilizing the odd-weight- column code, the implementation based on the proposed SEC-DED code with check bit pre-computation achieves reductions in the number of gates, latency, and power consumption of the ECC processing circuits by up to 9.3%, 18.4%, and 14.1% for 64 data bits in a word.
Ahmed, Belal,Jo, Hongil,Yoon, Sung Won,Choi, Kwang Yong,Ok, Kang Min Elsevier 2018 Journal of solid state chemistry Vol.267 No.-
<P><B>Abstract</B></P> <P>Four new transition metal oxyfluorides revealing chain structures composed of asymmetric basic building units of [MO<SUB>2</SUB>F<SUB>4</SUB>]<SUP>2−</SUP> (M = Mo and W) and [M’(pz/mpz)<SUB>4</SUB>]<SUP>2+</SUP> (M′ = Cu and Ni) polyhedra, i.e., [Cu(mpz)<SUB>4</SUB>][MoO<SUB>2</SUB>F<SUB>4</SUB>] (1), [Cu(pz)<SUB>4</SUB>]<SUB>2</SUB>[WO<SUB>2</SUB>F<SUB>4</SUB>]<SUB>2</SUB> (2), [Ni(pz)<SUB>4</SUB>]<SUB>2</SUB>[MoO<SUB>2</SUB>F<SUB>4</SUB>]<SUB>2</SUB> (3), and [Ni(pz)<SUB>4</SUB>][WO<SUB>2</SUB>F<SUB>4</SUB>] (4) (pz = pyrazole; mpz = 3-methyl pyrazole) have been synthesized via hydrothermal reactions. The linear chain structures found from the title compounds are attributable to the <I>trans</I>-directing [MO<SUB>2</SUB>F<SUB>4</SUB>]<SUP>2-</SUP> octahedral moiety and hydrogen bonding interactions. Strong Jahn–Teller distortions are observed for Cu<SUP>2+</SUP> cations with d<SUP>9</SUP> configuration in compounds 1 and 2. All the compounds show both lower-energy and higher-energy absorption band gaps, which originate from the <I>d</I>–<I>d</I> transitions and the distortion of octahedral geometry of M<SUP>2+</SUP> cations, respectively. The magnetism of [Cu(mpz)<SUB>4</SUB>][MoO<SUB>2</SUB>F<SUB>4</SUB>] turns out to be described by noninteracting Cu<SUP>2+</SUP> spins rather than a spin chain due to long exchange path mediated via the nonmagnetic Mo<SUP>6+</SUP> ions. The title compounds have been also thoroughly characterized using spectroscopic and thermal analyses along with calculations of local dipole moments and the extent of out-of-center distortions.</P> <P><B>Highlights</B></P> <P> <UL> <LI> Four novel oxyfluoride chain compounds with asymmetric units were synthesized in high yields. </LI> <LI> Detailed structural analysis influencing the geometry of chains have been analyzed. </LI> <LI> Magnetic properties and electron paramagnetic resonance spectroscopy on a representative material were investigated. </LI> <LI> Dipole moments and the extent of out-of-center distortions calculations were provided. </LI> </UL> </P> <P><B>Graphical abstract</B></P> <P>A series of oxyfluoride chains containing asymmetric basic building units of both early- and late-transition metal cations are reported.</P> <P>[DISPLAY OMISSION]</P>
Ki-Chul Chun,Jae-Yoon Sim,Hongil Yoon,Hyun-Seok Lee,Sang-Pyo Hong,Kyu-Chan Lee,Jei-Hwan Yoo,Dong-Il Seo 한국물리학회 2004 Current Applied Physics Vol.4 No.1
A 1.8 V low-voltage and low-power 128 Mb mobile SDRAM is designed and fabricated for hand-held, battery-operated elec-tronic devices with a 0.15-l m CMOS technology. As an essential low-voltage circuit, a triple pumping scheme is proposed togenerate a stable boosted voltage whose level exceeds over twice the supply voltage and which is required for the boosted word-linebias. In addition, to convert the bit-line data to a low-voltage CMOS level, a new NMOS and PMOS hybrid folded current senseamplier with dual-path current sensing scheme is proposed to obtain the stableI-to-V gain as well as to improve the low-voltage margin.
단위 셀 Reference 저항을 사용한 ReRAM용 Multi-Level Sense Amplifier
조문성(Moonsung Jo),윤홍일(Hongil Yoon) 대한전자공학회 2010 대한전자공학회 학술대회 Vol.2010 No.6
A novel reference resistor scheme is proposed for ReRAM multi-level sense amplifier. Only one ReRAM cell is used as a reference resistor instead of four ReRAM cells. Compared to the conventional scheme, the implementations using the proposed scheme achieve 34% power savings without the increase of read time. Also, the proposed scheme enhances tolerance for the variation of voltage sources, capacitors, and cell resistance.
A Low-Power ECC Check Bit Generator Implementation in DRAMs
Sang-Uhn Cha,Yun-Sang Lee,Hongil Yoon 대한전자공학회 2006 Journal of semiconductor technology and science Vol.6 No.4
A low-power ECC check bit generator is presented with competent DRAM implementation with minimal speed loss, area overhead and power consumption. The ECC used in the proposed scheme is a variant form of the minimum weight column code. The spatial and temporal correlations of input data are analyzed and the input paths of the check bit generator are ordered for the on-line adaptable power savings up to 24.4% in the benchmarked cases. The chip size overhead is estimated to be under 0.3% for a 80㎚ 1Gb DRAM implementation.