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Die-to-Die Parasitic Extraction Targeting Face-to-Face Bonded 3D ICs
Song, Taigon,Lim, Sung Kyu The Korea Institute of Information and Commucation 2015 Journal of information and communication convergen Vol.13 No.3
Face-to-face (F2F) bonding in three-dimensional integrated circuits (3D ICs), compared with other bonding styles, is closer to commercialization because of its benefits in terms of density, yield, and cost. However, despite the benefits that F2F bonding expect to provide, it's physical nature has not been studied thoroughly. In this study, we, for the first time, extract cross-die (inter-die) parasitic elements from F2F bonds on the full-chip scale and compare them with the intra-die elements. This allows us to demonstrate the significant impact of field sharing across dies in F2F bonding on full-chip noise and critical path delay values. The baseline method used is the die-by-die method, where the parasitic elements of individual dies are extracted separately and the cross-die parasitic elements are ignored. Compared with this inaccurate method, which was the only method available until now, our first-of-its-kind holistic method corrects the delay error by 25.48% and the noise error by 175%.
Full-Chip Power/Performance Benefits of Carbon Nanotube-Based Circuits
Song, Taigon,Lim, Sung Kyu The Korea Institute of Information and Commucation 2015 Journal of information and communication convergen Vol.13 No.3
As a potential alternative to the complementary metal-oxide semiconductor (CMOS) technology, many researchers are focusing on carbon-nanotube field-effect transistors (CNFETs) for future electronics. However, existing studies report the advantages of CNFETs over CMOS at the device level by using small-scale circuits, or over outdated CMOS technology. In this paper, we propose a methodology of analyzing CNFET-based circuits and study its impact at the full-chip scale. First, we design CNFET standard cells and use them to construct large-scale designs. Second, we perform parasitic extraction of CNFET devices and characterize their timing and power behaviors. Then, we perform a full-chip analysis and show the benefits of CNFET over CMOS in 45-nm and 20-nm designs. Our full-chip study shows that in the 45-nm design, CNFET circuits achieve a 5.91×/3.87× (delay/power) benefit over CMOS circuits at a density of 200 CNTs/µm. In the 20-nm design, CNFET achieves a 6.44×/3.01× (delay/power) benefit over CMOS at a density of 200 CNTs/µm.
Full-Chip Signal Integrity Analysis and Optimization of 3-D ICs
Taigon Song,Chang Liu,Yarui Peng,Sung Kyu Lim IEEE 2016 IEEE transactions on very large scale integration Vol.24 No.5
<P>Through-silicon-via (TSV)-to-TSV coupling is a new phenomenon in 3-D ICs, and it becomes a significant source of signal integrity problems. The existing studies on its extraction and analysis, however, become inaccurate when handling more than two TSVs on full-chip scale. In this paper, we investigate the multiple TSV-to-TSV coupling issue and propose a model that can be efficiently used for full-chip extraction. Then, we perform an analysis on the impact of TSV parasitics on coupling and delay. Unlike the common belief that only the closest neighboring TSVs affect the victim, this paper shows that nonneighboring aggressors also cause nonnegligible coupling noise. Based on these observations, we propose an effective method of reducing the overall coupling level.</P>
Modeling and Analysis of Through-Silicon Via (TSV) Noise Coupling and Suppression Using a Guard Ring
Jonghyun Cho,Eakhwan Song,Kihyun Yoon,Jun So Pak,Joohee Kim,Woojin Lee,Taigon Song,Kiyeong Kim,Junho Lee,Hyungdong Lee,Kunwoo Park,Seungtaek Yang,Minsuk Suh,Kwangyoo Byun,Joungho Kim IEEE 2011 IEEE transactions on components, packaging, and ma Vol.1 No.2
<P>In three-dimensional integrated circuit (3D-IC) systems that use through-silicon via (TSV) technology, a significant design consideration is the coupling noise to or from a TSV. It is important to estimate the TSV noise transfer function and manage the noise-tolerance budget in the design of a reliable 3D-IC system. In this paper, a TSV noise coupling model is proposed based on a three-dimensional transmission line matrix method (3D-TLM). Using the proposed TSV noise coupling model, the noise transfer functions from TSV to TSV and TSV to the active circuit can be precisely estimated in complicated 3D structures, including TSVs, active circuits, and shielding structures such as guard rings. To validate the proposed model, a test vehicle was fabricated using the Hynix via-last TSV process. The proposed model was successfully verified by frequency- and time-domain measurements. Additionally, a noise isolation technique in 3D-IC using a guard ring structure is proposed. The proposed noise isolation technique was also experimentally demonstrated; it provided -17 dB and -10dB of noise isolation between the TSV and an active circuit at 100 MHz and 1 GHz, respectively.</P>
안승영(Seungyoung Ahn),송대건(Taigon Song),이희재(Heejae Lee),변정건(Jung-Gun Byun),강덕수(Deogsoo Kang),최철승(Cheol-Seung Choi),조동호(Dong-Ho Cho),김정호(Joungho Kim) 대한전기학회 2010 대한전기학회 학술대회 논문집 Vol.2010 No.7
최근 개발된 온라인 전기자동차는, 도로면 아래에 매설된 급전선로에 의해 발생된 자기장을 차량 하부에 설치된 집전장치로 전달하고 이를 차량의 동력원으로 사용하는 새로운 방식의 전기자동차이다. 기존의 전기자동차에 비해 배터리의 용량을 1/5 수준으로 감소시킴으로써, 전기자동차의 무게와 가격을 감소시키고, 충전소 설치와 운영에 관한 문제점을 근본적으로 해결할 수 있다는 장점을 가진다. 본 논문에서는, 온라인 전기자동차의 개념과 효율적인 비접촉식 자기장 전달 방식을 소개하고, 급전장치와 집전장치 사이의 강한 자기장의 전달을 유지하면서 외부로 누설되는 자기장이 최소화할 수 있는 기술을 설명한다. 실제로 전파법이 정하는 규격을 만족시킨 서울대공원 코끼리열차 사례를 통해 향후 온라인 전기자동차의 자기장 차폐 기술의 방향에 대해 논한다.
High-Frequency Scalable Electrical Model and Analysis of a Through Silicon Via (TSV)
Joohee Kim,Jun So Pak,Jonghyun Cho,Eakhwan Song,Jeonghyeon Cho,Heegon Kim,Taigon Song,Junho Lee,Hyungdong Lee,Kunwoo Park,Seungtaek Yang,Min-Suk Suh,Kwang-Yoo Byun,Joungho Kim IEEE 2011 IEEE transactions on components, packaging, and ma Vol.1 No.2
<P>We propose a high-frequency scalable electrical model of a through silicon via (TSV). The proposed model includes not only the TSV, but also the bump and the redistribution layer (RDL), which are additional components when using TSVs for 3-D integrated circuit (IC) design. The proposed model is developed with analytic <I>RLGC</I> equations derived from the physical configuration. Each analytic equation is proposed as a function of design parameters of the TSV, bump, and RDL, and is therefore, scalable. The scalability of the proposed model is verified by simulation from the 3-D field solver with parameter variations, such as TSV diameter, pitch between TSVs, and TSV height. The proposed model is experimentally validated through measurements up to 20 GHz with fabricated test vehicles of a TSV channel, which includes TSVs, bumps, and RDLs. Based on the proposed scalable model, we analyze the electrical behaviors of a TSV channel with design parameter variations in the frequency domain. According to the frequency-domain analysis, the capacitive effect of a TSV is dominant under 2 GHz. On the other hand, as frequency increases over 2 GHz, the inductive effect from the RDLs becomes significant. The frequency dependent loss of a TSV channel, which is capacitive and resistive, is also analyzed in the time domain by eye-diagram measurements. Due to the frequency dependent loss, the voltage and timing margins decrease as the data rate increases.</P>
NS3K : A 3nm Nanosheet FET Library for VLSI Prediction in Advanced Nodes
Taehak Kim,Jaehoon Jeong,Seungmin Woo,Jeonggyu Yang,Hyunwoo Kim,Ahyeon Nam,Changdong Lee,Jinmin Seo,Minji Kim,Siwon Ryu,Yoonju Oh,Taigon Song 대한전자공학회 2021 대한전자공학회 학술대회 Vol.2021 No.6
Nanosheet FETs (NSFETs) are expected as future devices that replace FinFETs beyond the 5nm node. Despite the importance of the devices, few studies report the impact of NSFETs in the full-chip level. Therefore, this paper presents NS3K, the first 3nm NSFET library, and presents the results in a full-chip scale. Based on our results, 3nm NSFET reduces power by -27.4%, total wirelength by -25.8%, number of cells by -8.5%, and area by -47.6% over 5nm FinFET, respectively, due to better devices and interconnect scaling. However, careful device/layout designs followed by routing-resource considering standard cells are required to maximize the advantages of 3nm technology.