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32-bit RISC-V상에서의 경량 블록암호 PIPO 최적 병렬 구현
엄시우 ( Si-woo Eum ),장경배 ( Kyung-bae Jang ),송경주 ( Gyeong-ju Song ),이민우 ( Min-woo Lee ),서화정 ( Hwa-jeong Seo ) 한국정보처리학회 2021 한국정보처리학회 학술대회논문집 Vol.28 No.2
PIPO 경량 블록암호는 ICISC‘20에서 발표된 암호이다. 본 논문에서는 PIPO의 단일 평문 최적화 구현과 4평문 병렬 구현을 제안한다. 단일 평문 최적화 구현은 Rlayer의 최적화와 키스케쥴을 포함하지 않은 구현을 진행하였다. 결과적으로 키스케쥴을 포함하는 기존 연구 대비 70%의 성능 향상을 확인하였다. 4평문의 경우 32-bit 레지스터를 최대한 활용하여, 레지스터 내부 정렬과 Rlayer의 최적화 구현을 진행하였다. 또한 Addroundkey 구현에서 메모리 최적화 구현과 속도 최적화 구현을 나누어 구현하였다. 메모리 사용을 줄인 메모리 최적화 구현은 단일 평문 구현 대비 80%의 성능 향상을 확인하였고, 암호화 속도를 빠르게 구현한 속도 최적화 구현은 단일 평문 구현 대비 157%의 성능 향상을 확인하였다.
Switching pMOS Sense Amplifier for High-Density Low-Voltage Single-Ended SRAM
Hanwool Jeong,Taewon Kim,Kyoman Kang,Taejoong Song,Gyuhong Kim,Hyo-sig Won,Seong-Ook Jung IEEE 2015 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 1 R Vol.62 No.6
<P>A switching pMOS sense amplifier (SPSA) is proposed for high-speed single-ended static RAM sensing. By using the same pull-up pMOS transistor for sensing and precharging the bit-line, the performance is enhanced, and the power consumption is reduced. A keeper that compensates bit-line leakage is also employed, and a minimum operating voltage of 0.51 V is obtained. Compared to the previous dynamic pMOS sense amplifier and AC-coupled sense amplifier (ACSA), the sensing time is improved by 55% and 10%, respectively, and the power consumption is reduced by 12% and 44%, respectively. Furthermore, the area of the SPSA is estimated to be 43% smaller than that of the ACSA. Although the SPSA has a 59% larger area than a dynamic pMOS sense amplifier, the area overhead can be mitigated by allocating a larger number of cells per bit-line (CpBL) because the performance of the SPSA is still better than that of the dynamic pMOS, even with a CpBL that is two times larger.</P>
Hanwool Jeong,Taewon Kim,Younghwi Yang,Taejoong Song,Gyuhong Kim,Hyo-sig Won,Seong-Ook Jung IEEE 2015 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 1 R Vol.62 No.4
<P>An offset-compensated cross-coupled PFET bit-line (BL) conditioning circuit (OC-CPBC) and a selective negative BL write-assist circuit (SNBL-WA) are proposed for high-density FinFET static RAM (SRAM). The word-line (WL) underdrive read-assist and the negative BL write-assist circuits should be used for the stable operation of high-density FinFET SRAM. However, the WL underdrive read-assist circuit degrades the performance, and the negative BL write-assist circuit consumes a large amount of energy. The OC-CPBC enhances BL development during the evaluation phase by applying cross-coupled PFETs whose offset is compensated by precharging each of the two BLs separately through diode-connected cross-coupled PFETs. The SNBL-WA performs a write assist only when a write failure is detected, and this selective write assist reduces the write energy consumption. The simulation results show that the performance and energy consumption are improved by 41% and 48%, respectively, by applying the OC-CPBC and SNBL-WA to SRAM, even with a decrease in area.</P>
Bitline Precharging and Preamplifying Switching pMOS for High-Speed Low-Power SRAM
Jeong, Hanwool,Park, Juhyun,Oh, Tae Woo,Rim, Woojin,Song, Taejoong,Kim, Gyuhong,Won, Hyo-Sig,Jung, Seong-Ook IEEE 2016 IEEE Transactions on Circuits and Systems II: Expr Vol. No.
<P>A pMOS transistor with a switch is used for two purposes in a differential bitline: precharging and preamplifying during a read operation. These functions are realized by alternately changing the connection of the drain of the switching pMOS according to the operating mode. By using the same pMOS for precharging and preamplifying, the variability of a sense amplifier can be tracked, which can effectively reduce the bitline swing for the read operation. Moreover, because of the lowered bitline precharge level in the proposed scheme, the read stability is improved, as compared with that of the conventional scheme. Thus, a higher wordline voltage can be used to further improve the speed. Consequently, the delay and energy in the bitline are reduced by 1.85-5.88 times and 35%-70%, respectively, according to the supply voltage and number of cells per bitline, with a negligible area overhead of 0.9%.</P>