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Yongsik Kim,Minkyung Bae,Woojoon Kim,Dongsik Kong,Hyun Kwang Jung,Hyungtak Kim,Sunwoong Kim,Dong Myong Kim,Dae Hwan Kim IEEE 2012 IEEE transactions on electron devices Vol.59 No.10
<P>A combination of the multifrequency <I>C</I>- <I>V</I> and the generation-recombination current spectroscopy is proposed for a complete extraction of density of states (DOS) in amorphous InGaZnO thin-film transistors (a-IGZO TFTs) over the full subband-gap energy range (<I>EV</I> ≤ <I>E</I> ≤ <I>EC</I>) including the interface trap density between the gate oxide and the a-IGZO active layer. In particular, our result on the separate extraction of acceptor- and donor-like DOS is noticeable for a systematic design of amorphous oxide semiconductor TFTs because the former determines their dc characteristics and the latter does their threshold voltage (<I>VT</I>) instability under practical operation conditions. The proposed approach can be used to optimize the fabrication process of thin-film materials with high mobility and stability for mass-production-level amorphous oxide semiconductor TFTs.</P>
Sunwoong Kim,Yuseong Choi,박진영,성덕현 대한재활의학회 2016 Annals of Rehabilitation Medicine Vol.40 No.5
Spinal dural arteriovenous fistulas (SDAVFs) are the most common type of spinal vascular malformations. However, SDAVFs are still underdiagnosed entities because their clinical symptoms are usually non-specific, as they include low back pain or radiating pain to the limb. There have been several reports of acute paraplegia after lumbar epidural steroid injections in patients with SDAVFs. We present 4 patients with SDAVFs who received lumbar steroid injection. Among the 4 cases, acute paraplegia developed in 2 cases that received a larger volume of injectate than the other cases. Thus, we are suggesting that the volume of injectate may be a contributing factor for acute paraplegia after lumbar steroid injection in patients with SDAVFs.
Evaluation on Low-floor Bus Package Layout from the Perspective of Universal Design
Sunwoong Kim,Ji Yeon Kim,Hwan Hwangbo,Bong-Ha Hwang,Yong Joo Moon,Young Gu Ji 대한인간공학회 2011 大韓人間工學會誌 Vol.30 No.5
Objective: The aim of this study is to suggest a package layout guideline for low-floor bus by interview with passengers and observations of their behavior. Background: Increasing attention has been introduced the low-floor bus to be more suitable for use by transportation handicapped. Complex issues are involved in providing comfortable services to all people. We are going to suggest package layout guidelines for more comfortable and suitable travel to all people. Method: The two times of survey and video observation sessions were conducted on low-floor buses in Seoul; (1) a finding of potential issues in the first session, (2) a confirming of issues from the last session. Results: The three of major issues were founded in this study; (1) difficulties in supporting body when standing, (2) difficulties in sitting on front wheel pan seat, (3) difficulties in passing through the aisle. Conclusion: There were clear differences between public and transportation handicapped in using some tools which are used for support body such as roof hand rails, side hand rails, and hand rail rings. Some of design problems were founded to improve from the perspective of ergonomics and universal design. Such differences and design guidelines have to be considered in bus design as well as commercial vehicle. Application: The proposed design guidelines can be used to development of low-floor bus and other public transportations.
Fine-scalable SPIHT Hardware Design for Frame Memory Compression in Video Codec
Sunwoong Kim,Ji Hun Jang,Hyuk-Jae Lee,Chae Eun Rhee 대한전자공학회 2017 Journal of semiconductor technology and science Vol.17 No.3
In order to reduce the size of frame memory or bus bandwidth, frame memory compression (FMC) recompresses reconstructed or reference frames of video codecs. This paper proposes a novel FMC design based on discrete wavelet transform (DWT) - set partitioning in hierarchical trees (SPIHT), which supports fine-scalable throughput and is area-efficient. In the proposed design, multi-cores with small block sizes are used in parallel instead of a single core with a large block size. In addition, an appropriate pipelining schedule is proposed. Compared to the previous design, the proposed design achieves the processing speed which is closer to the target system speed, and therefore it is more efficient in hardware utilization. In addition, a scheme in which two passes of SPIHT are merged into one pass called merged refinement pass (MRP) is proposed. As the number of shifters decreases and the bit-width of remained shifters is reduced, the size of SPIHT hardware significantly decreases. The proposed FMC encoder and decoder designs achieve the throughputs of 4,448 and 4,000 Mpixels/s, respectively, and their gate counts are 76.5K and 107.8K. When the proposed design is applied to high efficiency video codec (HEVC), it achieves 1.96% lower average BDBR and 0.05 ㏈ higher average BDPSNR than the previous FMC design.
Optimized Interpolation and Cached Data Access in LUT-Based RGB-to-RGBW Conversion
Kim, Sunwoong,Lee, Hyuk-Jae IEEE 2018 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 2 E Vol.65 No.7
<P>In recent display panels, the RGBW color domain becomes popular because it improves the brightness of the display panel compared to the conventional RGB domain. An RGBW display system, in general, uses a look-up table (LUT) for fast RGB-to-RGBW conversion. However, a large-sized LUT is implemented in external memory, which slows down system speed and increases power consumption. For robust LUT-based RGB-to-RGBW conversion, this brief proposes two schemes. First, the data mapping of the LUT is sub-sampled. For fast conversion, the sub-sampled data are approximately interpolated. Moreover, the interpolation performance is improved by using a refinement scheme. Second, a small internal buffer that caches the information from the LUT is used for the conversion. When the information stored in the buffer is used for conversion, the access to the LUT of the external memory is skipped, thereby reducing the execution time during RGB-to-RGBW conversion. Experimental results show that the average of mean squared errors by the proposed sub-sampling and interpolation schemes varies from 0.00 to 21.72 when the quantization step is changed from 1 to 5, respectively. Compared to the trilinear interpolation, the proposed interpolation scheme reduces the number of accesses to the LUT from 8 to 2 and that of linear interpolation executions from 7 to 1. The proposed caching scheme with a 2.2 KB buffer reduces the execution time by 81.93%.</P>
Fine-scalable SPIHT Hardware Design for Frame Memory Compression in Video Codec
Kim, Sunwoong,Jang, Ji Hun,Lee, Hyuk-Jae,Rhee, Chae Eun The Institute of Electronics and Information Engin 2017 Journal of semiconductor technology and science Vol.17 No.3
In order to reduce the size of frame memory or bus bandwidth, frame memory compression (FMC) recompresses reconstructed or reference frames of video codecs. This paper proposes a novel FMC design based on discrete wavelet transform (DWT) - set partitioning in hierarchical trees (SPIHT), which supports fine-scalable throughput and is area-efficient. In the proposed design, multi-cores with small block sizes are used in parallel instead of a single core with a large block size. In addition, an appropriate pipelining schedule is proposed. Compared to the previous design, the proposed design achieves the processing speed which is closer to the target system speed, and therefore it is more efficient in hardware utilization. In addition, a scheme in which two passes of SPIHT are merged into one pass called merged refinement pass (MRP) is proposed. As the number of shifters decreases and the bit-width of remained shifters is reduced, the size of SPIHT hardware significantly decreases. The proposed FMC encoder and decoder designs achieve the throughputs of 4,448 and 4,000 Mpixels/s, respectively, and their gate counts are 76.5K and 107.8K. When the proposed design is applied to high efficiency video codec (HEVC), it achieves 1.96% lower average BDBR and 0.05 dB higher average BDPSNR than the previous FMC design.