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Contact Resistance of Inkjet-Printed Silver Source–Drain Electrodes in Bottom-Contact OTFTs
Seungjun Chung,Jaewook Jeong,Donghyun Kim,Yunhwan Park,Changhee Lee,Yongtaek Hong IEEE 2012 Journal of display technology Vol.8 No.1
<P>In this paper, we report contact resistance analysis between inkjet-printed silver source-drain (S/D) electrodes and organic semiconductor layer in bottom-contact organic thin-film transistors (OTFTs) using transmission line method (TLM). Inkjet-printed silver electrodes, spin-coated PVP and evaporated pentacene were used as gate and S/D electrodes, gate dielectric layer and semiconductor layer, respectively. On a common gate electrode, S/D electrodes with various channel length from 15 to 111 m were printed for TLM analysis. The same bottom-contact OTFT with evaporated silver S/D electrodes was also fabricated for reference. We extracted contact resistances of 1.79 M cm and 0.55 M cm for inkjet-printed and evaporated silver electrodes, respectively. Higher contact resistance for inkjet-printed silver electrodes can be explained in terms of their relatively poor surface properties at electrode edge that can cause small pentacene molecule grain or slight oxidation of surface during the printed silver sintering process.</P>
A Fully Integrated Dual-Band WLP CMOS Power Amplifier for 802.11n WLAN Applications
Seungjun Baek,Hyunjin Ahn,Hyunsik Ryu,Ilku Nam,Deokgi An,Doo-Hyouk Choi,Mun-Sub Byun,Minsu Jeong,Bo-Eun Kim,Ockgoo Lee 한국전자파학회JEES 2017 Journal of Electromagnetic Engineering and Science Vol.17 No.1
A fully integrated dual-band CMOS power amplifier (PA) is developed for 802.11n WLAN applications using wafer-level package (WLP) technology. This paper presents a detailed design for the optimal impedance of dual-band PA (2 GHz/5 GHz PA) output transformers with low loss, which is provided by using 2:2 and 2:1 output transformers for the 2 GHz PA and the 5 GHz PA, respectively. In addition, several design issues in the dual-band PA design using WLP technology are addressed, and a design method is proposed. All considerations for the design of dual-band WLP PA are fully reflected in the design procedure. The 2 GHz WLP CMOS PA produces a saturated power of 26.3 dBm with a peak power-added efficiency (PAE) of 32.9%. The 5 GHz WLP CMOS PA produces a saturated power of 24.7 dBm with a PAE of 22.2%. The PA is tested using an 802.11n signal, which satisfies the stringent error vector magnitude (EVM) and mask requirements. It achieved an EVM of -28 dB at an output power of 19.5 dBm with a PAE of 13.1% at 2.45 GHz and an EVM of -28 dB at an output power of 18.1 dBm with a PAE of 8.9% at 5.8 GHz.
Flexible memristive memory array on plastic substrates.
Kim, Seungjun,Jeong, Hu Young,Kim, Sung Kyu,Choi, Sung-Yool,Lee, Keon Jae American Chemical Society 2011 Nano letters Vol.11 No.12
<P>The demand for flexible electronic systems such as wearable computers, E-paper, and flexible displays has recently increased due to their advantages over present rigid electronic systems. Flexible memory is an essential part of electronic systems for data processing, storage, and communication and thus a key element to realize such flexible electronic systems. Although several emerging memory technologies, including resistive switching memory, have been proposed, the cell-to-cell interference issue has to be overcome for flexible and high performance nonvolatile memory applications. This paper describes the development of NOR type flexible resistive random access memory (RRAM) with a one transistor-one memristor structure (1T-1M). By integration of a high-performance single crystal silicon transistor with a titanium oxide based memristor, random access to memory cells on flexible substrates was achieved without any electrical interference from adjacent cells. The work presented here can provide a new approach to high-performance nonvolatile memory for flexible electronic applications.</P>
쇄석다짐말뚝에 발생하는 간극막힘 저감방안에 관한 수치해석적 연구
정재원(Jaewon Jeong),이승준(Seungjun Lee),박노원(Nowon Park),천병식(Byungsik Chun) 한국지반환경공학회 2013 한국지반환경공학회논문집 Vol.14 No.1
현재 연약지반 처리에 있어 장기침하 및 부등침하, 지지력 부족으로 인한 지반 전단파괴 및 허용 침하량 초과 등과 같은 지반공학적 문제점들을 보완하고자 연약지반의 침하 저감 및 지지력 증대, 압밀촉진을 목적으로 SCP 공법과 GCP 공법이 대표적으로 적용되고 있다. 그러나 압밀촉진효과 즉, 두 다짐말뚝의 배수능 차이에 대해서는 아직 충분히 규명되지 않을 뿐 아니라 특히 실무에서는 GCP 공법의 간극막힘 현상을 최소화시키기 위한 노력으로 소정 비율의 모래를 혼입하여 다짐말뚝을 적용하고 있지만, 이 또한 정량적으로 명확하게 규명되어 있지 않고 경험적인 방법으로 수행되고 있는 실정에 있다. 따라서 본 연구에서는 SCP와 GCP, GCP에 소정의 모래를 혼합한 형태의 공법에 대한 압밀촉진효과를 비교 · 평가하기 위하여 각각의 다짐말뚝이 적용된 복합지반에 먼저 대형직접전단시험을 수행하여 큰 지지력을 나타낼 것으로 기대되는 배합비를 산정하여, PFC3D를 활용한 개별요소법과 MIDAS GTS를 활용한 유한요소해석을 수행하여 간극막힘 현상을 저감할 수 있는 방안을 제시하고자 한다. 대형직접전단시험 결과, 배합비쇄석:모래가 70:30에서 가장 큰 지지력이 기대되는 것으로 추정되며 수치해석을 수행한 결과, 기존 쇄석다짐말뚝에 소정의 모래를 혼입함으로써 지지력 확보와 간극막힘 현상 저감 및 간극수를 더 빨리 배출하여 연약지반을 더 빨리 안정화할 수 있을 것으로 사료된다. Recently, engineering problems such as long-term settlement, differential settlement, and the resultant structural damage, have been frequently reported at construction sites. Use of Sand Compaction Piles(SCP) and Granular Compaction Piles(GCP) are good at remedying existing problems, improving bearing capacity and promoting consolidation. However, such compaction piles have the potential for clogging, which would limit their usability. Investigations into the potential for clogging in SCP, GCP, and GCP mixed with sand has not been thoroughly conducted and is the objective of this current study. Large scale direct shear tests were performed on sections of SCP, GCP, and sand mixed GCP to evaluate bearing capacity. Discrete Element Method analyses were conducted with PFC3D and Finite Element Analyses were conducted with MIDAS GTS to propose an algorithm to help reduce clogging in the granular compaction piles. Results from the large scale direct shear test and multiple simulations suggest a 70% gravel and 30%sand mixing ratio to be optimal for bearing capacity and reducing clogging.