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( Ching-ling Lin ),( Ming-lin Tsai ),( Yu-hsin Chen ),( Wei-ni Liu ),( Chun-yu Lin ),( Kai-wen Hsu ),( Chien-yu Huang ),( Yu-jia Chang ),( Po-li Wei ),( Shu-huey Chen ),( Li-chi Huang ),( Chia-hwa Lee 한국응용약물학회 2021 Biomolecules & Therapeutics(구 응용약물학회지) Vol.29 No.5
Thyroid cancer is the most common endocrine malignancy. Patients with well-differentiated thyroid cancers, such as papillary and follicular cancers, have a favorable prognosis. However, poorly differentiated thyroid cancers, such as medullary, squamous and anaplastic advanced thyroid cancers, are very aggressive and insensitive to radioiodine treatment. Thus, novel therapies that attenuate metastasis are urgently needed. We found that both PDGFC and PDGFRA are predominantly expressed in thyroid cancers and that the survival rate is significantly lower in patients with high PDGFRA expression. This finding indicates the important role of PDGF/PDGFR signaling in thyroid cancer development. Next, we established a SW579 squamous thyroid cancer cell line with 95.6% PDGFRA gene insertion and deletions (indels) through CRISPR/Cas9. Protein and invasion analysis showed a dramatic loss in EMT marker expression and metastatic ability. Furthermore, xenograft tumors derived from PDGFRA geneedited SW579 cells exhibited a minor decrease in tumor growth. However, distant lung metastasis was completely abolished upon PDGFRA gene editing, implying that PDGFRA could be an effective target to inhibit distant metastasis in advanced thyroid cancers. To translate this finding to the clinic, we used the most relevant multikinase inhibitor, imatinib, to inhibit PDGFRA signaling. The results showed that imatinib significantly suppressed cell growth, induced cell cycle arrest and cell death in SW579 cells. Our developed noninvasive apoptosis detection sensor (NIADS) indicated that imatinib induced cell apoptosis through caspase-3 activation. In conclusion, we believe that developing a specific and selective targeted therapy for PDGFRA would effectively suppress PDGFRA-mediated cancer aggressiveness in advanced thyroid cancers.
Lin, Ching-Kun,Chen, Hsien-Ching,Li, Rong-Kwei,Chen, Ching-Piao,Tsai, Chih-Hung The Korean Society for Quality Management 2009 The Asian Journal on Quality Vol.10 No.1
Face the process yield rate improvements of motherboard, although general enterprises finish deployment goal of each functions by overall quality managements, through quality improvement methods, industry engineering methods, plan-do-check-act (PDCA) methods and other improvement solutions, but it is only can be improved partially and unable to enhance the yield rate of product to the target. It only can takes one step ahead to enhance the process yield rate of motherboard with six sigma ($6{\sigma}$) overall DMAIC process and tactics. This research aimed to use six sigma quality improvement tactics by DMAIC systematic procedure and tactics, and find the key factors that effect to the process yield rate of surface mount technology. It also identified the keys input and process and output index to satisfy customer requirements and internal process index. The results showed that the major effective factors by fishbone and process failure modes and effects analysis (PFMEA). If the index of input and output that can be quantified, the optimum parameter can be found through design of experiment to ensure that the process is stable. If the factor of input and output that cannot be quantified, we found out the effective countermeasure by Mind_Mapping, make sure whole processes can be controlled stably, to reach the high product quality and enhance the customer satisfaction.
A 3-Gb/s Equalizer with an Adaptive Swing Controller for TFT-LCD Interfaces
Miao-Shan Li,Yen-Chen Lin,Chai-Chi Liu,Ching-Rong Chang,Jyun-Yi Li,You-Sheng Lin,Ching-Yuan Yang 대한전자공학회 2019 Journal of semiconductor technology and science Vol.19 No.1
A 0.18-μm CMOS 3-Gb/s equalizer with an adaptive swing controller is presented for 4K2K large display panels to compensate a 24-dB channel loss. Employing the output-swing control technique, we propose the adaptive loop for the equalizer to improve adaptation accuracy without degrading the boost tuning and input swing ranges. Besides, cascading two bandpass filters (BPF) measured energy in a narrow range is much more accuracy than conventional highpass filters (HPF). The measured jitter of 3-Gb/s and 1.5-Gb/s data are 0.23-UI and 0.356-UI for 1.23-m FR4 board, respectively. The core area occupies 0.12-㎟ and the power consumption is 27-mW at 3 Gb/s from a 1.8-V supply.
Composting and trickling filter for treatment of olive mill waste
Li, Xinhua,Lin, Ching-Chieh,Sweeney, Daniel,Earl, Jessica,Hong, Andy Techno-Press 2013 Advances in environmental research Vol.2 No.2
Agricultural practice and improper waste disposal in developing regions have resulted in environmental degradation in land and waters, for which low-cost, proven solutions are needed. We demonstrate in the laboratory the applications of composting and trickling filter techniques to treat olive mill wastes that can be implemented in the West Bank and other regions of the world. To a pomace waste sample from a California mill, we amended with saw dust (wood carbon source) and baking soda ($NaHCO_3$ alkalinity) at weight ratios of waste/wood/$NaHCO_3$ at 70:27:1 and composted it for periods of 11 and 48 days; the compost was used as an additive to potting soil for transplanting. The pomace sample was also blended into slurry and introduced to a water-circulating pond and trickling filter system (P/TF) to examine any inhibitive effect of the pomace on biological removal of the organic waste. The results showed the compost-amended potting soil supported plant growth without noticeable stress over 34 days and the P/TF system removed BOD and COD by >90% from the waste liquid within 2 days, with a first-order rate constant of 1.9 $d^{-1}$ in the pond. An onsite treatment design is proposed that promises implementation for agricultural waste disposal in developing regions.
Parallel-Plate Capacitor Structures with Enhanced Linearity
Ching-Lieh Li,Chih-Wei Hsueh,Ding-Kai Lin 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
In this paper, the FDTD method is employed to calculate the static capacitance of several parallel-plate capacitors. The study of the capacitor characteristics is made to emphasis on the linearity analysis for the possible sensor application. The linearity of several parallel-plate structures is examined, which include a simple parallelplate capacitor, a parallel-plate structure with guard ring only, etc. Although the guard ring is usually utilized to increase the linearity of a simple parallel-plate capacitor, it is found that the linearity of a parallel-plate capacitor with guard ring is actually the same as a simple parallel-plate capacitor with the same plate area. Afterwards, a new parallel-plate structure with pins inserted in between the parallel plates is proposed to reduce the linearity deviation as the separation of the parallel plates changes.
Lin, Yu-Cheng,Tsai, Chih-Hung,Li, Rong-Kwei,Chen, Ching-Piao,Chen, Hsien-Ching The Korean Society for Quality Management 2008 The Asian Journal on Quality Vol.9 No.3
The definition of cycle time is the time from the wafer start to the wafer output. It usually takes one or two months to get the product since customer decides to produce it. The cycle time is a critical factor for customer satisfaction because it represents the response time to the market. Long cycle time reflects the ineffective investment for the capital. The cycle time is very important for foundry because long cycle time will cause customer unsatisfied and the order loss. Consequently, all of the foundries put lots of human source in the cycle time improvement. Usually, we make decisions based on the experience in the cycle time management. We have no mechanism or theory for cycle time management. We do work-in-process (WIP) management based on turn rate and standard WIP (STD WIP) set by experiences. But the experience didn't mean the optimal solution, when the situation changed, the cycle time or the standard WIP will also be changed. The experience will not always be applicable. If we only have the experience and no mechanism, management will not be work out. After interview several foundry fab managers, all of the fab can't reflect the situation. That is, all of them will have an impact period after product mix or utilization varied. In this study, we want to develop a formula for standard WIP and use statistical process control (SPC) concept to set WIP upper/lower limit level. When WIP exceed the limit level, it will trigger action plans to compensate WIP Profile. If WIP Profile balances, we don't need too much WIP. So WIP level could be reduced and cycle time also could be reduced.