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Crisp, Ryan W.,Pach, Gregory F.,Kurley, J. Matthew,France, Ryan M.,Reese, Matthew O.,Nanayakkara, Sanjini U.,MacLeod, Bradley A.,Talapin, Dmitri V.,Beard, Matthew C.,Luther, Joseph M. American Chemical Society 2017 Nano letters Vol.17 No.2
<P>We developed a monolithic CdTe–PbS tandem solar cell architecture in which both the CdTe and PbS absorber layers are solution-processed from nanocrystal inks. Due to their tunable nature, PbS quantum dots (QDs), with a controllable band gap between 0.4 and ∼1.6 eV, are a promising candidate for a bottom absorber layer in tandem photovoltaics. In the detailed balance limit, the ideal configuration of a CdTe (<I>E</I><SUB>g</SUB> = 1.5 eV)–PbS tandem structure assumes infinite thickness of the absorber layers and requires the PbS band gap to be 0.75 eV to theoretically achieve a power conversion efficiency (PCE) of 45%. However, modeling shows that by allowing the thickness of the CdTe layer to vary, a tandem with efficiency over 40% is achievable using bottom cell band gaps ranging from 0.68 and 1.16 eV. In a first step toward developing this technology, we explore CdTe–PbS tandem devices by developing a ZnTe–ZnO tunnel junction, which appropriately combines the two subcells in series. We examine the basic characteristics of the solar cells as a function of layer thickness and bottom-cell band gap and demonstrate open-circuit voltages in excess of 1.1 V with matched short circuit current density of 10 mA/cm<SUP>2</SUP> in prototype devices.</P><P><B>Graphic Abstract</B> <IMG SRC='http://pubs.acs.org/appl/literatum/publisher/achs/journals/content/nalefd/2017/nalefd.2017.17.issue-2/acs.nanolett.6b04423/production/images/medium/nl-2016-04423k_0006.gif'></P><P><A href='http://pubs.acs.org/doi/suppl/10.1021/nl6b04423'>ACS Electronic Supporting Info</A></P>
DIMM-in-a-PACKAGE Memory Device Technology for Mobile Applications
Crisp, R. The Korean Microelectronics and Packaging Society 2012 마이크로전자 및 패키징학회지 Vol.19 No.4
A family of multi-die DRAM packages was developed that incorporate the full functionality of an SODIMM into a single package. Using a common ball assignment analogous to the edge connector of an SODIMM, a broad range of memory types and assembly structures are supported in this new package. In particular DDR3U, LPDDR3 and DDR4RS are all supported. The center-bonded DRAM use face-down wirebond assembly, while the peripherybonded LPDDR3 use the face-up configuration. Flip chip assembly as well as TSV stacked memory is also supported in this new technology. For the center-bonded devices (DDR3, DDR4 and LPDDR3 ${\times}16$ die) and for the face up wirebonded ${\times}32$ LPDDR3 devices, a simple manufacturing flow is used: all die are placed on the strip in a single machine insertion and are sourced from a single wafer. Wirebonding is also a single insertion operation: all die on a strip are wirebonded at the same time. Because the locations of the power signals is unchanged for these different types of memories, a single consolidated set of test hardware can be used for testing and burn-in for all three memory types.
Experimental investigation of Scalability of DDR DRAM packages
Crisp, R. The Korean Microelectronics and Packaging Society 2010 마이크로전자 및 패키징학회지 Vol.17 No.4
A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded $microBGA^{(R)}$. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.
진영희,I. Nicholas Crispe,박선 연세대학교의과대학 2005 Yonsei medical journal Vol.46 No.6
Hepatocytes are the primary targets of the hepatitis C virus (HCV). While immunosuppressive roles of HCV core protein have been found in several studies, it remains uncertain whether core protein expressed in hepatocytes rather than in immune cells affects the CD8+ T cell response. In order to transduce genes selectively into hepatocytes, we developed a baculoviral vector system that enabled primary hepatocytes to express a target epitope for CD8+ T cells, derived from ovalbumin (OVA), with or without HCV core protein. Culture of OVA-specific CD8+ T cells with hepatocytes infected with these baculoviral vectors revealed that core protein has no effect on proliferation or apoptosis of CD8+ T cells. Our results suggest that HCV core protein does not exert its suppressive role on the CD8+ T cell immune response through expression in hepatocytes.