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10 nm-Ni 층과 비정질 실리콘층으로 제조된 저온공정 나노급 니켈실리사이드의 물성 변화
최용윤 ( Young Youn Choi ),박종성 ( Jong Sung Park ),송오성 ( Oh Sung Song ) 대한금속재료학회 ( 구 대한금속학회 ) 2009 대한금속·재료학회지 Vol.47 No.5
60 nm- and 20 nm-thick hydrogenated amorphous silicon (a-Si:H) layers were deposited on 200 nm SiO2/Si substrates using ICP-CVD (inductively coupled plasma chemical vapor deposition). A 10 nm-Ni layer was then deposited by e-beam evaporation. Finally, 10 nm-Ni/60 nm a-Si:H/200 nm-SiO2/Si and 10 nm-Ni/20 nm a-Si:H/200 nm-SiO2/Si structures were prepared. The samples were annealed by rapid thermal annealing for 40 seconds at 200~500℃ to produce NiSi(x). The resulting changes in sheet resistance, microstructure, phase, chemical composition and surface roughness were examined. The nickel silicide on a 60 nm a-Si:H substrate showed a low sheet resistance at T (temperatures) >450℃. The nickel silicide on the 20 nm a-Si:H substrate showed a low sheet resistance at T>300℃. HRXRD analysis revealed a phase transformation of the nickel silicide on a 60 nm a-Si:H substrate (δ-Ni2Si→ζ-Ni2Si→(NiSi+ζ-Ni2Si)) at annealing temperatures of 300℃→400℃→500℃. The nickel silicide on the 20 nm a-Si:H substrate had a composition of δ-Ni2Si with no secondary phases. Through FE-SEM and TEM analysis, the nickel silicide layer on the 60 nm a-Si:H substrate showed a 60 nm-thick silicide layer with a columnar shape, which contained both residual a-Si:H and Ni2Si layers, regardless of annealing temperatures. The nickel silicide on the 20 nm a-Si:H substrate had a uniform thickness of 40 nm with a columnar shape and no residual silicon. SPM analysis shows that the surface roughness was<1.8 nm regardless of the a-Si:H-thickness. It was confirmed that the low temperature silicide process using a 20 nm a-Si:H substrate is more suitable for thin film transistor (TFT) active layer applications. (Received January 19, 2009)
Catalytic CVD 저온공정으로 제조된 나노급 니켈실리사이드의 물성
최용윤 ( Yong Yoon Choi ),김건일 ( Kun Il Kim ),박종성 ( Jong Sung Park ),송오성 ( Oh Sung Song ) 대한금속·재료학회 2010 대한금속·재료학회지 Vol.48 No.2
10 nm thick Ni layers were deposited on 200 nm SiO2/Si substrates using an e-beam evaporator. Then, 60 nm or 20 nm thick α-Si:H layers were grown at low temperature (<200℃) by a Catalytic-CVD. NiSi layers were already formed instantaneously during Cat-CVD process regardless of the thickness of the α-Si. The resulting changes in sheet resistance, microstructure, phase, chemical composition, and surface roughness with the additional rapid thermal annealing up to 500℃ were examined using a four point probe, HRXRD, FE-SEM, TEM, AES, and SPM, respectively. The sheet resistance of the NiSi layer was 12Ω/□ regardless of the thickness of the α-Si and kept stable even after the additional annealing process. The thickness of the NiSi layer was 30 nm with excellent uniformity and the surface roughness was maintained under 2 nm after the annealing. Accordingly, our result implies that the low temperature Cat-CVD process with proposed films stack sequence may have more advantages than the conventional CVD process for nano scale NiSi applications.
Practical channel prediction for NR and LTE massive MIMO using hybrid Kalman filters
Yongyun Choi(최용윤),Yang Li,Ying Wang 한국통신학회 2021 한국통신학회 학술대회논문집 Vol.2021 No.2
Accurate channel state information (CSI) is critical for optimal throughput of massive MIMO (mMIMO) systems. Out-of-date CSI due to user mobility causes significant throughput degradation, which is a known industry-wide challenge. In this paper, we propose a novel and practical solution for CSI prediction by using hybrid Kalman filters where both parametric and non-parametric estimations are applied. Up to 80% throughput gain has been shown in extensive system-level and link-level simulation. The proposed algorithm has achieved noticeable gain using extensive field data captured from commercial mMIMO systems. Various algorithm complexity reduction has been done to enable a proof-of-concept development using commercialized mMIMO system.
한정조,송오성,최용윤,Han, Jeung-Jo,Song, Oh-Sung,Choi, Young-Youn 한국재료학회 2009 한국재료학회지 Vol.19 No.4
We fabricated thermally evaporated 30 nm-Ni/(20 nm or 60 nm)a-Si:H/Si films to investigate the energy-saving property of silicides formed by rapid thermal annealing (RTA) at temperatures of $350^{\circ}C$, $450^{\circ}C$, $550^{\circ}C$, and $600^{\circ}C$ for 40 seconds. A transmission electron microscope (TEM) and a high resolution X-ray diffractometer (HRXRD) were used to determine the cross-sectional microstructure and phase changes. A UVVIS-NIR and FT-IR (Fourier transform infrared spectroscopy) were employed for near-IR and middle-IR absorbance. Through TEM and HRXRD analysis, for the nickel silicide formed at low temperatures below $450^{\circ}C$, we confirmed columnar-shaped structures with thicknesses of $20{\sim}30\;nm$ that had ${\delta}-Ni^2Si$ phases. Regarding the nickel silicide formed at high temperatures above $550^{\circ}C$, we confirmed that the nickel silicide had more than 50 nm-thick columnar-shaped structures with a $Ni_{31}Si_{12}$ phase. Through UV-VIS-NIR analysis, nickel silicide showed almost the same absorbance in the near IR region as well as ITO. However, in the middle IR region, the nickel silicides with low temperature showed similar absorbance to those from high temperature silicidation.
60 nm 와 20 nm 두께의 수소화된 비정질 실리콘에 따른 저온 니켈실리사이드의 물성 변화
김종률,박종성,최용윤,송오성,Kim, Joung-Ryul,Park, Jong-Sung,Choi, Young-Youn,Song, Oh-Sung 한국진공학회 2008 Applied Science and Convergence Technology Vol.17 No.6
ICP-CVD를 사용하여 수소화된 비정질 실리콘(a-Si:H)을 60 nm 또는 20 nm 두께로 성막 시키고, 그 위에 전자총증착장치(e-beam evaporator)를 이용하여 30 nm Ni 증착 후, 최종적으로 30 nm Ni/(60 또는 20 nm a-Si:H)/200 nm $SiO_2$/single-Si 구조의 시편을 만들고 $200{\sim}500^{\circ}C$ 사이에서 $50^{\circ}C$간격으로 40초간 진공열처리를 실시하여 실리사이드화 처리하였다. 완성된 니켈실리사이드의 처리온도에 따른 면저항값, 상구조, 미세구조, 표면조도 변화를 각각 사점면저항측정기, HRXRD, FE-SEM과 TEM, SPM을 활용하여 확인하였다. 60 nm a-Si:H 기판 위에 생성된 니켈실리사이드는 $400^{\circ}C$이후부터 저온공정이 가능한 면저항값을 보였다. 반면 20 nm a-Si:H 기판 위에 생성된 니켈실리사이드는 $300^{\circ}C$이후부터 저온공정이 가능한 면저항값을 보였다. HRXRD 결과 60 nm 와 20 nm a-Si:H 기판 위에 생성된 니켈실리사이드는 열처리온도에 따라서 동일한 상변화를 보였다. FE-SEM과 TEM 관찰결과, 60 nm a-Si:H 기판 위에 생성된 니켈실리사이드는 저온에서 고저항의 미반응 실리콘이 잔류하고 60 nm 두께의 니켈실리사이드를 가지는 미세구조를 보였다. 20 nm a-Si:H 기판위에 형성되는 니켈실리사이드는 20 nm 두께의 균일한 결정질 실리사이드가 생성됨을 확인하였다. SPM 결과 모든 시편은 열처리온도가 증가하면서 RMS값이 증가하였고 특히 20 nm a-Si:H 기판 위에 생성된 니켈실리사이드는 $300^{\circ}C$에서 0.75 nm의 가장 낮은 RMS 값을 보였다. 60 nm and 20 nm thick hydrogenated amorphous silicon(a-Si:H) layers were deposited on 200 nm $SiO_2$/single-Si substrates by inductively coupled plasma chemical vapor deposition(ICP-CVD). Subsequently, 30 nm-Ni layers were deposited by an e-beam evaporator. Finally, 30 nm-Ni/(60 nm and 20 nm) a-Si:H/200 nm-$SiO_2$/single-Si structures were prepared. The prepared samples were annealed by rapid thermal annealing(RTA) from $200^{\circ}C$ to $500^{\circ}C$ in $50^{\circ}C$ increments for 40 sec. A four-point tester, high resolution X-ray diffraction(HRXRD), field emission scanning electron microscopy(FE-SEM), transmission electron microscopy(TEM), and scanning probe microscopy(SPM) were used to examine the sheet resistance, phase transformation, in-plane microstructure, cross-sectional microstructure, and surface roughness, respectively. The nickel silicide from the 60 nm a-Si:H substrate showed low sheet resistance from $400^{\circ}C$ which is compatible for low temperature processing. The nickel silicide from 20 nm a-Si:H substrate showed low resistance from $300^{\circ}C$. Through HRXRD analysis, the phase transformation occurred with silicidation temperature without a-Si:H layer thickness dependence. With the result of FE-SEM and TEM, the nickel silicides from 60 nm a-Si:H substrate showed the microstructure of 60 nm-thick silicide layers with the residual silicon regime, while the ones from 20 nm a-Si:H formed 20 nm-thick uniform silicide layers. In case of SPM, the RMS value of nickel silicide layers increased as the silicidation temperature increased. Especially, the nickel silicide from 20 nm a-Si:H substrate showed the lowest RMS value of 0.75 at $300^{\circ}C$.
폴리이미드 기판에 극저온 Catalytic-CVD로 제조된 니켈실리사이드와 실리콘 나노박막
송오성 ( Oh Sung Song ),최용윤 ( Yong Yoon Choi ),한정조 ( Jung Jo Han ),김건일 ( Gun Il Kim ) 대한금속재료학회(구 대한금속학회) 2011 대한금속·재료학회지 Vol.49 No.4
The 30 nm-thick Ni layers was deposited on a flexible polyimide substrate with an e-beam evaporation. Subsequently, we deposited a Si layer using a catalytic CVD (Cat-CVD) in a hydride amorphous silicon (α-Si:H) process of Ts=180℃ with varying thicknesses of 55, 75, 145, and 220 nm. The sheet resistance, phase, degree of the crystallization, microstructure, composition, and surface roughness were measured by a four-point probe, HRXRD, micro-Raman spectroscopy, FE-SEM, TEM, AES, and SPM. We confirmed that our newly proposed Cat-CVD process simultaneously formed both NiSi and crystallized Si without additional annealing. The NiSi showed low sheet resistance of <13Ω/□, while carbon (C) diffused from the substrate led the resistance fluctuation with silicon deposition thickness. HRXRD and micro-Raman analysis also supported the existence of NiSi and crystallized (>66%) Si layers. TEM analysis showed uniform NiSi and silicon layers, and the thickness of the NiSi increased as Si deposition time increased. Based on the AES depth profiling, we confirmed that the carbon from the polyimide substrate diffused into the NiSi and Si layers during the Cat-CVD, which caused a pile-up of C at the interface. This carbon diffusion might lessen NiSi formation and increase the resistance of the NiSi.